Address decoding within SOC

Within an SOC that has multiple processors connected via AXI buses,
where does the address decoding logic reside? If there are peripherals
like a UART that are shared between the processors, would they have to
be memory mapped at the same address in the address space of both
processors? This is why I am asking where the address decoding logic
resides.

Thanks.

joshc wrote:

> Within an SOC that has multiple processors connected via AXI buses,
> where does the address decoding logic reside? If there are peripherals
> like a UART that are shared between the processors, would they have to
> be memory mapped at the same address in the address space of both
> processors? This is why I am asking where the address decoding logic
> resides.
> 
> Thanks.

I think you are asking the wrong question, apologies if I'm wrong.
It's not about "what address?" (could be the same or different) or "where
resides?" (could be distributed - along the CPU cores -  or concentrated -
with the shared resource). What you need to realise (should have asked) is:
Q. how multiprocessor systems share resources?
The short answer:
A. they must make use of an _arbiter_ module that makes the resource busy
when one processor (master) use it, so that the others wait their turn.
Protocols to get access, priorities...

Adrian

On Jun 17, 6:20 pm, Adrian Spilca <adsp40@spamGuard_yahoo.co.uk>
wrote:
> joshc wrote:
> > Within an SOC that has multiple processors connected via AXI buses,
> > where does the address decoding logic reside? If there are peripherals
> > like a UART that are shared between the processors, would they have to
> > be memory mapped at the same address in the address space of both
> > processors? This is why I am asking where the address decoding logic
> > resides.
>
> > Thanks.
>
> I think you are asking the wrong question, apologies if I'm wrong.
> It's not about "what address?" (could be the same or different) or "where
> resides?" (could be distributed - along the CPU cores -  or concentrated -
> with the shared resource). What you need to realise (should have asked) is:
> Q. how multiprocessor systems share resources?

</snip>

Actually, I meant what I asked. Given a shared peripheral, where does
the address decoding take place. In other words, is the address
decoding done in one place so both processors would have to generate
the same address on the bus to access the peripheral? Or, is the
address decoder sometimes intelligent and depending on what CPU puts
the address out on the bus, it generates a chip select accordingly so
that a shared peripheral can be mapped differently within the address
space of the corresponding CPUs? Or, is there some other mechanism?

joshc wrote:
> Within an SOC that has multiple processors connected via AXI buses,
> where does the address decoding logic reside? If there are peripherals
> like a UART that are shared between the processors, would they have to
> be memory mapped at the same address in the address space of both
> processors? This is why I am asking where the address decoding logic
> resides.
> 
> Thanks.
> 

Hi there,

The decoding implementation depends on what type of AXI interconnection
infrastructure you are using.  If you are using the ARM PrimeCell AXI
Configurable Interconnect (PL300), then the decoding is done inside the
PL300 itself.  For each bus master interface inside PL300, there is an
address decoder.   For multiple master system, there are multiple
of these address decoder and they have the same address decoing function.

(See section 2.3 of http://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)

Please notice that peripherals like UART will be more likely to be
put on an APB bus.  You can connect an AXI to APB bridge to a PL300
and then attach multiple peripherals to it.  For the decoding of 
multiple APB devices, sometimes a separated APB decoder could be used,
but there is also APB bridge designs that integrated an address decoder.

Regarding what Adrian was looking at, each AXI slave interface has an 
arbiter (also a part of the PL300).
(See section 2.1.4 of 
http://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)

regards,
Joseph

On Jun 18, 7:28 am, Joseph <joseph....@somewhere-in-arm.com> wrote:
> joshc wrote:
> > Within an SOC that has multiple processors connected via AXI buses,
> > where does the address decoding logic reside? If there are peripherals
> > like a UART that are shared between the processors, would they have to
> > be memory mapped at the same address in the address space of both
> > processors? This is why I am asking where the address decoding logic
> > resides.
>
> > Thanks.
>
> Hi there,
>
> The decoding implementation depends on what type of AXI interconnection
> infrastructure you are using.  If you are using the ARM PrimeCell AXI
> Configurable Interconnect (PL300), then the decoding is done inside the
> PL300 itself.  For each bus master interface inside PL300, there is an
> address decoder.   For multiple master system, there are multiple
> of these address decoder and they have the same address decoing function.
>
> (See section 2.3 ofhttp://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)
>
> Please notice that peripherals like UART will be more likely to be
> put on an APB bus.  You can connect an AXI to APB bridge to a PL300
> and then attach multiple peripherals to it.  For the decoding of
> multiple APB devices, sometimes a separated APB decoder could be used,
> but there is also APB bridge designs that integrated an address decoder.
>
> Regarding what Adrian was looking at, each AXI slave interface has an
> arbiter (also a part of the PL300).
> (See section 2.1.4 ofhttp://www.arm.com/pdfs/DDI0354B_aci_pl300_r0p1_trm.pdf)
>
> regards,
> Joseph

That's exactly the information I was looking for. I'm just a software
person as you can tell. Thanks for the pointers to that information!