Hello every one,
We have designed a board which
contains an ALTERA fpga and an EPROM(EPC2LC20).The design is done with
respect to some existing reference schematics.We have populated our
PCB so as to get the power to all the components and then we have
placed the components making up the JTAG circuitary along with the
FPGA and EPROM.
,Altera's Byte blaster is being used
which is working fine. have checked all the circuitary which seems to
be alright but we keep getting the error"Unable to access the JTAG
chain".We have also tried the steps in the ALTERAs trouble shooters.
Do we need to proceed in a different
way while programming the chip/EPROM for the first time.And also what
is the passive serial mode in the Quartus tool for programming. Any
help would be highly appreciated.Thanks in advance.
New board JTAG error
Started by ●July 11, 2007
Reply by ●July 12, 20072007-07-12
mailsatishv@gmail.com wrote:> Hello every one, > We have designed a board which > contains an ALTERA fpga and an EPROM(EPC2LC20).The design is done with > respect to some existing reference schematics.We have populated our > PCB so as to get the power to all the components and then we have > placed the components making up the JTAG circuitary along with the > FPGA and EPROM. > ,Altera's Byte blaster is being used > which is working fine. have checked all the circuitary which seems to > be alright but we keep getting the error"Unable to access the JTAG > chain".We have also tried the steps in the ALTERAs trouble shooters. > Do we need to proceed in a different > way while programming the chip/EPROM for the first time.And also what > is the passive serial mode in the Quartus tool for programming. Any > help would be highly appreciated.Thanks in advance.comp.arch.embedded is probably less relevant than comp.arch.fpga. Please see my response there in case you only monitor comp.arch.embedded rather than both.
