Forums

USART design consideration

Started by tguclu July 17, 2007
Hi everyone ,i'm new to group.
In my project i need  to use 3xUSART ports in order to build a SDLC
network. USART ports will function as the phy of SDLC as V.24
Anyway , this is not the point.

Each USART will work at 64kbps. So there is a network traffic of
almost 192 kps. The problem ise my cpu board doesn't have 2x UART but
no USART port so i have use a microcontroller with at least 3xUSART
and 1xUART to communicate with cpu board.


One of the candidate is M16C/62P group of Renesas which   can operate
max. of 24Mhz .

Can you explain me what is the relationship with the CPU's clock freq.
and Baudrate of the UART module ?

Thanks..

tguclu wrote:

> Can you explain [to] me what is the relationship [between] the CPU's
> clock freq. and Baudrate of the UART module ? Typically the UART can be clocked by either an external clock signal or the divided down processor clock. In the latter case, the UART normally needs either 8x or 16x the bit rate. The baud rate generator will divide the internal processor clock by a programmed integer value to supply as the UART clock. If the clock frequency is an exact multiple of 16x (or 8x, depending on the processor) the baud rate, you should be fine. For asynchronous transfer, the system will usually work if the baud rate matches the other unit within about 3%. Thad -- Thad
tguclu wrote:
> Hi everyone ,i'm new to group. > In my project i need to use 3xUSART ports in order to build a SDLC > network. USART ports will function as the phy of SDLC as V.24 > Anyway , this is not the point. > > Each USART will work at 64kbps. So there is a network traffic of > almost 192 kps. The problem ise my cpu board doesn't have 2x UART but > no USART port so i have use a microcontroller with at least 3xUSART > and 1xUART to communicate with cpu board. > > > One of the candidate is M16C/62P group of Renesas which can operate > max. of 24Mhz . > > Can you explain me what is the relationship with the CPU's clock freq. > and Baudrate of the UART module ? > > Thanks.. >
Yes. If f_b is the baud rate, and f_c is the CPU clock, then they are related by f_b = A * f_c. A can be any real number from 0 to infinity, although it is usually a rational fraction from 0 to infinity. But that's not what you need to know. What you really need to know is what baud rate can your particular processor handle, and whether your particular processor has the computing power to shove all the bytes around to the correct places when they come in. Baud rate is nearly always related to the system clock by some rational fraction. I doubt that it'll be hard to get 64kbps out of the thing with the right clock going in, but just how much you'll have to constrain the processor clock to get that is something you'll have to check. Processing power is also related to the system clock by some rational fraction. You really can't relate a processor's speed directly to it's clock rate -- some processors with really efficient pipelines average more than 1 MIPS / MHz, while some older processors take 12 or more clocks per instruction. What you're trying to do is build an SLDC bridge to your 'main' processor, or perhaps a concentrator. At any rate, what you need to be asking is what sort of resources it'll take to do the protocol conversions; then you'll need to try to translate that into what the Renasas chip is capable of. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
On Jul 17, 3:50 pm, tguclu <tugrul.gu...@gmail.com> wrote:
> Hi everyone ,i'm new to group. > In my project i need to use 3xUSART ports in order to build a SDLC > network. USART ports will function as the phy of SDLC as V.24 > Anyway , this is not the point. > > Each USART will work at 64kbps. So there is a network traffic of > almost 192 kps. The problem ise my cpu board doesn't have 2x UART but > no USART port so i have use a microcontroller with at least 3xUSART > and 1xUART to communicate with cpu board. > > One of the candidate is M16C/62P group of Renesas which can operate > max. of 24Mhz . > > Can you explain me what is the relationship with the CPU's clock freq. > and Baudrate of the UART module ? > > Thanks..
Hi, The Baud rate is derived from the CPU clock frequency, PRE-SCALER and related SFRs . If you have data sheets of any microcontroller, you will be able to find it in UART/USART section. -Dk
On Jul 17, 5:50 am, tguclu <tugrul.gu...@gmail.com> wrote:
> Hi everyone ,i'm new to group. > In my project i need to use 3xUSART ports in order to build a SDLC > network. USART ports will function as the phy of SDLC as V.24 > Anyway , this is not the point. > > Each USART will work at 64kbps. So there is a network traffic of > almost 192 kps. The problem ise my cpu board doesn't have 2x UART but > no USART port so i have use a microcontroller with at least 3xUSART > and 1xUART to communicate with cpu board. > > One of the candidate is M16C/62P group of Renesas which can operate > max. of 24Mhz . > > Can you explain me what is the relationship with the CPU's clock freq. > and Baudrate of the UART module ? > > Thanks..
I've never worked with SDLC, but I know that it's a _synchronous_ link, _not_ an asynchrounous link. Therefore, a character is 8-bits long, and there are no start and stop chars. A 1x clock is generated somewhere in the system and is connected to each USART's transmit and receive clock pins. At 64kbps, a char will be received every 125 us (8 MHz rate). However, data is sent in blocks, so there won't be a constant stream of characters being sent and received. Your CPU must keep up with this data rate. I've had experience working with Zilog's Z8530 (SCC) and Z85230 (ESCC) for both aysnc and bi-sync links. Both chips were programmer "unfriendly", although the ESCC is slightly better. Many of the registers are write-only, so to change a bit in a reg I couldn't read the reg, change a bit, and update the reg. I had to keep a RAM copy, and first update the RAM copy and then write the reg. What a pain : ( So although both chips do SDLC, they wouldn't be my first choice! -Dave Pollum
On Tue, 17 Jul 2007 03:50:03 -0700, tguclu <tugrul.guclu@gmail.com>
wrote:

>Hi everyone ,i'm new to group. >In my project i need to use 3xUSART ports in order to build a SDLC >network. USART ports will function as the phy of SDLC as V.24 >Anyway , this is not the point. > >Each USART will work at 64kbps. So there is a network traffic of >almost 192 kps. The problem ise my cpu board doesn't have 2x UART but >no USART port so i have use a microcontroller with at least 3xUSART >and 1xUART to communicate with cpu board. > > >One of the candidate is M16C/62P group of Renesas which can operate >max. of 24Mhz . > >Can you explain me what is the relationship with the CPU's clock freq. >and Baudrate of the UART module ?
The "nice" SSCs which can do HDLC/SDLC etc. are getting hard to find, this type of functionality seems to be implemented in FPGAs these days. The STR7 ARM MCUs have got 3x USART of which 2 if I recall correctly can do HDLC at least. (Not sure about SDLC). The Baud rate of the UART Module is handled no differently in SDLC as in normal async mode. The only difference is that the clock is either embedded in the data stream of something like manchester encoding is used or each direction send a 1x Tx Clock as well as the data stream. The ST ARMs has got a fractional divider so you can get almost any baudrate you require from the range of CPU Clock frquencies supported. If the SCC you choose does not have a fractional divider then CPU clock can tipically only be divided by an integer number in the range 1 to 256 or sometimes 1 to 65536. Without a fractional divider you probably will have to provide a separate clock for your baud rate. Regards Anton Erasmus
On 21 Temmuz, 12:03, Anton Erasmus <nob...@spam.prevent.net> wrote:
> On Tue, 17 Jul 2007 03:50:03 -0700, tguclu <tugrul.gu...@gmail.com> > wrote: > > > > > > >Hi everyone ,i'm new to group. > >In my project i need to use 3xUSART ports in order to build a SDLC > >network. USART ports will function as the phy of SDLC as V.24 > >Anyway , this is not the point. > > >Each USART will work at 64kbps. So there is a network traffic of > >almost 192 kps. The problem ise my cpu board doesn't have 2x UART but > >no USART port so i have use a microcontroller with at least 3xUSART > >and 1xUART to communicate with cpu board. > > >One of the candidate is M16C/62P group of Renesas which can operate > >max. of 24Mhz . > > >Can you explain me what is the relationship with the CPU's clock freq. > >and Baudrate of the UART module ? > > The "nice" SSCs which can do HDLC/SDLC etc. are getting hard to find, > this type of functionality seems to be implemented in FPGAs these > days. The STR7 ARM MCUs have got 3x USART of which 2 if I recall > correctly can do HDLC at least. (Not sure about SDLC). > The Baud rate of the UART Module is handled no differently in SDLC as > in normal async mode. The only difference is that the clock is either > embedded in the data stream of something like manchester encoding is > used or each direction send a 1x Tx Clock as well as the data stream. > The ST ARMs has got a fractional divider so you can get almost any > baudrate you require from the range of CPU Clock frquencies supported. > If the SCC you choose does not have a fractional divider then CPU > clock can tipically only be divided by an integer number in the range > 1 to 256 or sometimes 1 to 65536. Without a fractional divider you > probably will have to provide a separate clock for your baud rate. > > Regards > Anton Erasmus- Al nt y gizle - > > - Al nt y g=F6ster -
Thanks everyone.Another question! Does any of you have the softcopy of GA27-3093-04 document of IBM (SDLC concepts)? Thanks