about HDLC/SDLC IC's

Hi
Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
you advice me ?
I'm undecided between Infineon 20542(2 Channel Serial Optimized
Communication Controller
with DMA-SEROCCO-D) and Zilog's Z85C30

What I need is ;
-3x USART outputs (i will have to use 2xIC's for that)
-SDLC protocol support
(prefer if bit stuffing,crc check,data flow control done in hw)


In the datasheet of Infineon 20542 , it says "The LAP controllers of
the two serial channels can be configured to function in a halfduplex
Normal Response Mode (NRM), where they operate as a slave (secondary)
station" which made me think that , we can't implement primary station
func. with this.

Any experience ?

Thanks

tguclu <tugrul.guclu@gmail.com> wrote:

> Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
> you advice me ?
> I'm undecided between Infineon 20542(2 Channel Serial Optimized
> Communication Controller
> with DMA-SEROCCO-D) and Zilog's Z85C30
> 
> What I need is ;
> -3x USART outputs (i will have to use 2xIC's for that)
> -SDLC protocol support
> (prefer if bit stuffing,crc check,data flow control done in hw)
> 
> 
> In the datasheet of Infineon 20542 , it says "The LAP controllers of
> the two serial channels can be configured to function in a halfduplex
> Normal Response Mode (NRM), where they operate as a slave (secondary)
> station" which made me think that , we can't implement primary station
> func. with this.

I haven't used the Infineon chip or read its data sheet but to me that
"can be configured" part implies this is an optional feature, and it
should be able to operate in "physical layer only" mode, which would
allow you to implement any HDLC/SDLC-like protocol on top of it,
including primary station standard HDLC/SDLC.

Actually implementing NRM in the chip is quite an advanced feature, as
it would need to handle all of the sequence numbering and other aspects.
This could be useful for some simple applications, but it depends on
what subset of HDLC it actually implements, and what degree of control
and interfacing you require.


All of what you ask is certainly possible with the Z85C30. We used the
Z85230 a while ago, which has several enhancements over the 'C30,
particularly in the area of FIFOs. We used it to implement both
bit-synchronous and asynchronous HDLC, both as primary and secondary
stations.

In bit-sync mode, the Z85C30/230 handles the physical layer: FLAG or
IDLE fill, bit stuffing and 16-bit CRC (using the standard CRC-CCITT
polynomial). It can also support frames which are not an exact multiple
of 8 bits.

It will recongise an ABORT sequence and can automatically abort a frame
on transmit for a data underrun.

It doesn't impose any interpretation on the content of a frame, except
for optionally treating the first 8 bits as an address field (only
receiving frames with a pre-programmed address, or a broadcast with
0xFF). You can turn this feature off if you want (e.g. for the primary
station). It may impose a minimum of four bytes per frame (address,
control, two CRC bytes), but that isn't a problem for standard HDLC/SDLC
frames.

I don't recall offhand whether it might have been possible to implement
CRC-32 in software, but I think this may have been achievable with the
'230 (the 'C30 doesn't deliver all the received bits to the host, losing
the last two bits of the CRC).

It supports a variety of bit-level encoding methods: NRZ, NRZI0, FM0,
FM1 and Manchester.

In async mode, you have to implement all HDLC features in software,
including insertion/deletion of CTRL-ESCAPE characters, CRC
calculations, etc.

In any mode, all HDLC data link layer aspects are handled in software.
The Z85C30/230 doesn't pay attention to the control field at all.

-- 
David Empson
dempson@actrix.gen.nz

On Tue, 07 Aug 2007 03:03:58 -0700, tguclu <tugrul.guclu@gmail.com>
wrote:

>Hi
>Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
>you advice me ?
>I'm undecided between Infineon 20542(2 Channel Serial Optimized
>Communication Controller
>with DMA-SEROCCO-D) and Zilog's Z85C30
>
>What I need is ;
>-3x USART outputs (i will have to use 2xIC's for that)
>-SDLC protocol support
>(prefer if bit stuffing,crc check,data flow control done in hw)
>
>
>In the datasheet of Infineon 20542 , it says "The LAP controllers of
>the two serial channels can be configured to function in a halfduplex
>Normal Response Mode (NRM), where they operate as a slave (secondary)
>station" which made me think that , we can't implement primary station
>func. with this.
>
>Any experience ?

The Zilog 16C30 is quite nice to use - MUCH easier than the Z85C30.

Regards
  Anton Erasmus

On 8 7 ,   7 03 , tguclu <tugrul.gu...@gmail.com> wrote:
> Hi
> Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
> you advice me ?
> I'm undecided between Infineon 20542(2 Channel Serial Optimized
> Communication Controller
> with DMA-SEROCCO-D) and Zilog's Z85C30
>
> What I need is ;
> -3x USART outputs (i will have to use 2xIC's for that)
> -SDLC protocol support
> (prefer if bit stuffing,crc check,data flow control done in hw)
>
> In the datasheet of Infineon 20542 , it says "The LAP controllers of
> the two serial channels can be configured to function in a halfduplex
> Normal Response Mode (NRM), where they operate as a slave (secondary)
> station" which made me think that , we can't implement primary station
> func. with this.
>
> Any experience ?
>
> Thanks

Hi,
I have used SIEMENS SAB82532 ic. It support HDLC/SDLC/BYTESync mode.
Speed is maybe  E1 grade(2048kbps). It is not difficult to handle.
Bye

On Fri, 10 Aug 2007 17:14:31 -0700, Frank Ryu <xwillow@naver.com>
wrote:

>On 8 7 ,   7 03 , tguclu <tugrul.gu...@gmail.com> wrote:
>> Hi
>> Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
>> you advice me ?
>> I'm undecided between Infineon 20542(2 Channel Serial Optimized
>> Communication Controller
>> with DMA-SEROCCO-D) and Zilog's Z85C30
>>
>> What I need is ;
>> -3x USART outputs (i will have to use 2xIC's for that)
>> -SDLC protocol support
>> (prefer if bit stuffing,crc check,data flow control done in hw)
>>
>> In the datasheet of Infineon 20542 , it says "The LAP controllers of
>> the two serial channels can be configured to function in a halfduplex
>> Normal Response Mode (NRM), where they operate as a slave (secondary)
>> station" which made me think that , we can't implement primary station
>> func. with this.
>>
>> Any experience ?
>>
>> Thanks
>
>Hi,
>I have used SIEMENS SAB82532 ic. It support HDLC/SDLC/BYTESync mode.
>Speed is maybe  E1 grade(2048kbps). It is not difficult to handle.
>Bye

The early silicon had a bug "feature" ? that prevented one from using
it in polled mode. The status flags did not update unless interrupts
for the specific status bit were enabled as well. 

Regards
  Anton Erasmus

I used M68302 many years ago.

tguclu wrote:
> Hi
> Does anyone used a peripheral IC for HDLC/SDLC implementation ? Can
> you advice me ?
> I'm undecided between Infineon 20542(2 Channel Serial Optimized
> Communication Controller
> with DMA-SEROCCO-D) and Zilog's Z85C30
>
> What I need is ;
> -3x USART outputs (i will have to use 2xIC's for that)
> -SDLC protocol support
> (prefer if bit stuffing,crc check,data flow control done in hw)
>
>
> In the datasheet of Infineon 20542 , it says "The LAP controllers of
> the two serial channels can be configured to function in a halfduplex
> Normal Response Mode (NRM), where they operate as a slave (secondary)
> station" which made me think that , we can't implement primary station
> func. with this.
>
> Any experience ?
>
> Thanks