Hi all , Can any one tell me a generic pattern to designing an interface between MCU(Configuring the Hardware ) and FPGA(used as an accelerator). My initial thoughts are to have a dual port RAM implemented in FPGA and accessed as a memory mapped device from the MCU and used to configure the Hardware. Is this viable ? is this the norm? Are there any tutorials on the net that can help(google didnt find any)? Any help will be appreciated ? BR Rate
Hardware (FPGA) Software(MCU) Interface
Started by ●September 12, 2007
Reply by ●September 12, 20072007-09-12
On Sep 12, 5:55 am, ratemonotonic <niladri1...@gmail.com> wrote:> Hi all , > > Can any one tell me a generic pattern to designing an interface > between MCU(Configuring the Hardware ) and FPGA(used as an > accelerator). > > My initial thoughts are to have a dual port RAM implemented in FPGA > and accessed as a memory mapped device from the MCU and used to > configure the Hardware. > > Is this viable ? is this the norm? Are there any tutorials on the net > that can help(google didnt find any)? > > Any help will be appreciated ? > > BR > RateGoogle "fpga coprocessor". More than a quarter-million hits. G.