Hello I want to connect a FPGA with uC to send some data (144 Mbits). My question is: Is there any parallel bus specification which I can use? Have you any recommendation? -- PGW posted to sci.electronics.design, comp.arch.embedded
Parallel bus
Started by ●October 5, 2007
Reply by ●October 5, 20072007-10-05
pgw wrote:> Hello > > I want to connect a FPGA with uC to send some data (144 Mbits). > My question is: Is there any parallel bus specification which I can use? > > Have you any recommendation? >144 Mbits per second ?? 144 Mbits per hour ?? 144 Mbits per year ??
Reply by ●October 5, 20072007-10-05
Donald wrote:> pgw wrote: > >> Hello >> >> I want to connect a FPGA with uC to send some data (144 Mbits). >> My question is: Is there any parallel bus specification which I can use? >> >> Have you any recommendation? >> > 144 Mbits per second ?? > > 144 Mbits per hour ?? > > 144 Mbits per year ??I need to send 144Mbits just once but it can't take a lot of time. I think reasonable time is 30sec also 4.8Mb/sec -- PGW
Reply by ●October 5, 20072007-10-05
pgw wrote:> Donald wrote: > > >>pgw wrote: >> >> >>>Hello >>> >>>I want to connect a FPGA with uC to send some data (144 Mbits). >>>My question is: Is there any parallel bus specification which I can use? >>> >>>Have you any recommendation? >>> >> >>144 Mbits per second ?? >> >>144 Mbits per hour ?? >> >>144 Mbits per year ?? > > > I need to send 144Mbits just once but it can't take a lot of time. > I think reasonable time is 30sec also 4.8Mb/sec >Ok, Lets say the bus is 8-bits wide. 144,000,000 / 8 = 18,000,000 bytes 18,000,000 / 30 seconds = 600,000 bytes per second 600,000 bytes/sec ~1.66 microseconds per byte Ok, where ever the 144Mbit is comming from needs to be stored, lets say RAM. How many micros have 18MBytes of RAM ? good luck, I have no ideas. don
Reply by ●October 5, 20072007-10-05
On Oct 5, 6:40 am, pgw <"SwietyMikolaj["@]poczta.onet.pl> wrote:> Donald wrote: > > pgw wrote: > > >> Hello > > >> I want to connect a FPGA with uC to send some data (144 Mbits). > >> My question is: Is there any parallel bus specification which I can use? > > >> Have you any recommendation? > > > 144 Mbits per second ?? > > > 144 Mbits per hour ?? > > > 144 Mbits per year ?? > > I need to send 144Mbits just once but it can't take a lot of time. > I think reasonable time is 30sec also 4.8Mb/sec >Build a SDRAM controller with your FPGA. While you are at it, build an ARM uC with your FPGA as well.
Reply by ●October 5, 20072007-10-05
Donald wrote:> pgw wrote: >> Donald wrote: >> >> >>>pgw wrote: >>> >>> >>>>Hello >>>> >>>>I want to connect a FPGA with uC to send some data (144 Mbits). >>>>My question is: Is there any parallel bus specification which I can use? >>>> >>>>Have you any recommendation? >>>> >>> >>>144 Mbits per second ?? >>> >>>144 Mbits per hour ?? >>> >>>144 Mbits per year ?? >> >> >> I need to send 144Mbits just once but it can't take a lot of time. >> I think reasonable time is 30sec also 4.8Mb/sec >> > Ok, Lets say the bus is 8-bits wide. > > 144,000,000 / 8 = 18,000,000 bytes > > 18,000,000 / 30 seconds = 600,000 bytes per second > > > 600,000 bytes/sec ~1.66 microseconds per byte > > Ok, where ever the 144Mbit is comming from needs to be stored, lets say RAM. > > How many micros have 18MBytes of RAM ? > > good luck, I have no ideas.I looking for some parallel bus specification (8 bits width max) to implement it on uC and FPGA. This bus I want to use to send some data with minimum 600 kbytes/sec data rate. Where I store this data is not the problem. Eventually I will invent some simple bus protocol but this is not the way. -- PGW
Reply by ●October 5, 20072007-10-05
>> Ok, Lets say the bus is 8-bits wide. >> >> 144,000,000 / 8 = 18,000,000 bytes >> >> 18,000,000 / 30 seconds = 600,000 bytes per second >> >> >> 600,000 bytes/sec ~1.66 microseconds per byte >> >> Ok, where ever the 144Mbit is comming from needs to be stored, lets say RAM. >> >> How many micros have 18MBytes of RAM ? >> >> good luck, I have no ideas. > > I looking for some parallel bus specification (8 bits width max) to > implement it on uC and FPGA. This bus I want to use to send some data with > minimum 600 kbytes/sec data rate. > > Where I store this data is not the problem. > > Eventually I will invent some simple bus protocol but this is not the way.Actually the data rate is not important, I'm just looking for example of simple parallel bus protocol. A clock I can just speed up to 1MHz. -- PGW
Reply by ●October 5, 20072007-10-05
linnix wrote:>> I need to send 144Mbits just once but it can't take a lot of time. >> I think reasonable time is 30sec also 4.8Mb/sec >> > > Build a SDRAM controller with your FPGA. While you are at it, build > an ARM uC with your FPGA as well.SDRAM is to complicated. And I don't need so big data throughput. But maybe I can use protocol from parallel flash or something like that, thanks for idea. Any ideas are still appreciate. -- PGW
Reply by ●October 5, 20072007-10-05
pgw wrote:> linnix wrote: > > >>>I need to send 144Mbits just once but it can't take a lot of time. >>>I think reasonable time is 30sec also 4.8Mb/sec >>> >> >>Build a SDRAM controller with your FPGA. While you are at it, build >>an ARM uC with your FPGA as well. > > > SDRAM is to complicated. And I don't need so big data throughput. > > But maybe I can use protocol from parallel flash or something like that, > thanks for idea. > > Any ideas are still appreciate. >I don't mean to be insulting here, but I think you have missed the ship. I don't think an off the shelf parallel bus protocol or specification is going to help you in the least and I don't think it is what you need. Instead, you first need to look at the hardware you intend to use or are using and see what resources are available to it. For example, does your uC support an external bus? Lets say for argument sake that it does. So, now you have a uC that will provide you with a set of data lines, address lines, and some form of read and write or read/write strobe, possibly some chip select lines. Now you need to look at the data sheet for the uC and and see what the timing paramaters of the device are as this will (be one of many things that) determine(s) your maximum through put rate. On the other end, you will need to look at the timing requirements of your receiver circuitry and see if the two are compatible. For example, do you have enough setup time and hold time before and after the read / write strobes? There are a lot of other factors that come in to play also such as what is the loading (especially the capacitance) compared to the drivers ability and do you have to derate the bus accordingly. You will also need to look at the electrical length of the bus lines and determine if they are going to work as a lumped or distributed circuit. If your trace length is long enough that the lines are behaving as transmission lines, if and how are you going to terminate them? I say if, because you could choose to let the address and data lines ring but then terminate the strobe signals while slowing the cycle time down. What I am getting at here is that you need to understard WHAT you are trying to do and HOW it will work. Trying to apply a canned solution without this fundamental understanding is doomed to failure. If you don't believe me and still want a an off the shelf solution then how about these picks: PC104, PC-AT, and PCI. Get a spec sheet and have at it. I do hope, though, that your logic analyzer is working and you have a really good scope becaus you WILL need them.
Reply by ●October 5, 20072007-10-05
On Fri, 05 Oct 2007 20:46:31 +0200, pgw wrote:> Where I store this data is not the problem. > > Eventually I will invent some simple bus protocol but this is not the way."Not the way"? Why? Is it a requirement from the teacher? Does it have to be bidirectional? Is there only one master and a slave, or can they both be masters/senders? It's almost trivial to design something like that. "I have data" "I'm ready for data" "Here's the data" [sends data] [receives data] "Got the data" [done] Nothing to it. You could look up, for example, the PC parallel port, but that's just hardware. The protocol is entirely up to you, which is what makes me suspect that this is homework. Good Luck! Rich
