Architecture question

Started by Tim Frink October 8, 2007

I've 3 questions about my Infineon TriCore microcontroller which is
described by Infineon as "32-bit microcontroller-DSP architecture
optimized for real-time embedded systems".

According to the manual, the DSP has the following memories:
·  Data Memory Unit (DMU) with
   ­ 64 Kbyte of Data Memory (SRAM)
   ­ 16 Kbyte of Stand-by Data Memory (SBRAM)
·  Program Memory Unit (PMU) with
   ­ 2 Mbyte of Program Flash Memory (PFLASH)
   ­ 128 Kbyte of Data Flash Memory (DFLASH)
   ­ 8 Kbyte of Boot ROM (BROM)
   ­ 8 Kbyte of Test ROM (TROM)
·  Program Memory Interface (PMI)
   ­ 48 Kbyte of Scratch-Pad RAM (SPRAM)
   ­ 16 Kbyte of Instruction Cache (ICACHE)
·  Data Memory Interface (DMI)
   ­ 56 Kbyte of Local Data RAM (LDRAM)
   ­ 8 Kbyte of Dual-Port RAM (DPRAM)
·  PCP memory
   ­ 32 Kbyte of PCP Code Memory (CMEM)
   ­ 16 Kbyte of PCP Data Memory (PRAM)

1) So, data can be either stored in DMU's SRAM or DMI's LDRAM which are
together 120 KByte (omitting the small special data memories). Is this
sufficient for a DSP in the embedded systems domain? I would expect that
typically significantly more data is processed.

2) Constant data can be also stored in the Data Flash Memory. Since the
Program Memory Unit can push its data through the instruction cache this
would mean that also constant data coming from the DFLASH is handled
equally as code (and can be stored in the ICACHE). I though in a harvard
architecture as found in the TriCore there's a strict distinction between
data and code. This seems, however, not to apply here.

2) I was surprised that the DSP comes with an instruction cache but
without a data cache. Is data caching not that important like caching
code for ES software? Or do you see any other reason why this cache
is missing here?

Thank you for your answer.