Testing Intel386EXTC microcontroller.

Hi,
    I have a designed a PCB that has a 512Kbits flash with Intel
386EXTC processor. I am trying to test my PCB by hooking up the data
and address lines on logic analyzer and writing simple JMP (short)
instruction in 386
assembly language. I know that since my UCS is connected to CS of
Flash, processor will go to FFF0h address of Flash and execute the
instruction present at FFF0h. My Flash contains  these simple
instructions:

ADD      Opcode
FFF0      EBh (opcode for short jump that takes 8 bit(here
05h)dispalcement)
FFF1      05h
FFF2      00h 
FFF3      00h 
FFF4      00h 
FFF5      00h 
FFF6      EBh 
FFF7      03h

On logic analyzer, I should see FFF5 after FFF0/FFF1. Instead, all I
see is addresses being incremented sequentially with whatever data is
present on the different locations ie I see EB,05 etc on data bus but
processor is not executing the instructions. I have tried other
instructions too, like NOP and HLT but can't seem to make my processor
do what it is asked to do. Can some one suggest what the problem may
be and how can I fix it? BS8 of processor is tied low.
Thanks

learner

"learner" <sonalsingh28@yahoo.com> wrote in message
news:40cfbbf5.0409150901.3e5df408@posting.google.com...
> Hi,
>     I have a designed a PCB that has a 512Kbits flash with Intel
> 386EXTC processor. I am trying to test my PCB by hooking up the data
> and address lines on logic analyzer and writing simple JMP (short)
> instruction in 386
> assembly language. I know that since my UCS is connected to CS of
> Flash, processor will go to FFF0h address of Flash and execute the
> instruction present at FFF0h. My Flash contains  these simple
> instructions:
>
> ADD      Opcode
> FFF0      EBh (opcode for short jump that takes 8 bit(here
> 05h)dispalcement)
> FFF1      05h
> FFF2      00h
> FFF3      00h
> FFF4      00h
> FFF5      00h
> FFF6      EBh
> FFF7      03h
>
> On logic analyzer, I should see FFF5 after FFF0/FFF1.

No, you should see FFF7. The 5 byte offset is added to the addres AFTER the
jump+offset instruction.

But as someone else already pointer out: what you see on the bus might not
show what the processor is doing. The CPU might read ahead while the code is
pipelined.

meindert