Hi, I have a PCB that has a 512Kbits flash with Intel 386EXTC processor. I am trying to test my PCB by hooking up the data and address lines on logic analyzer and writing simple JMP (short) instruction in 386 assembly language. I know that since my UCS is connected to CS of Flash, processor will go to FFF0h address of Flash and execute the instruction present at FFF0h. My Flash contains these simple instructions: ADD Opcode FFF0 EBh (opcode for short jump that takes 8 bit(here 05h)dispalcement) FFF1 05h FFF2 00h FFF3 00h FFF4 00h FFF5 00h FFF6 EBh FFF7 03h On logic analyzer, I should see FFF5 afetr FFF0/FFF1. Instead, all I see is addresses being incremented sequentially with whatever data is present on the different locations ie I see EB,05 etc on data bus but processor is not executing the instructions. I have tried other instructions too, like NOP and HLT but can't seem to make my processor do what it is asked to do. Can some one suggest what the problem may be and how can I fix it? Thanks learner
Intel 386EXTC boot up
Started by ●September 15, 2004
Reply by ●September 15, 20042004-09-15
In news:40cfbbf5.0409142217.3236dd52@posting.google.com, learner <sonalsingh28@yahoo.com> typed:> I have a PCB that has a 512Kbits flash with Intel 386EXTC processor. > I am trying to test my PCB by hooking up the data and address lines on > logic analyzer and writing simple JMP (short) instruction in 386 > assembly language. I know that since my UCS is connected to CS of > Flash, processor will go to FFF0h address of Flash and execute the > instruction present at FFF0h. My Flash contains these simple > instructions: > > ADD Opcode > FFF0 EBh (opcode for short jump that takes 8 bit(here > 05h)dispalcement) > FFF1 05h > FFF2 00h > FFF3 00h > FFF4 00h > FFF5 00h > FFF6 EBh > FFF7 03h > > On logic analyzer, I should see FFF5 afetr FFF0/FFF1. Instead, all I > see is addresses being incremented sequentially with whatever data is > present on the different locations ie I see EB,05 etc on data bus but > processor is not executing the instructions. I have tried other > instructions too, like NOP and HLT but can't seem to make my processor > do what it is asked to do. Can some one suggest what the problem may > be and how can I fix it?The 386EX prefetches instruction bytes ahead of the execution. It might well fetch five bytes after the jump instruction, which are then discarded when it restarts fetching from the jump destination. If it also fetches sequentially long after a longer jump, such as EBh 80h, the CPU, might not be reading the flash bytes correctly. Check that you pull BS8# low if your flash is 8-bit. Karl Olsen
Reply by ●September 15, 20042004-09-15
On 14 Sep 2004 23:17:25 -0700, sonalsingh28@yahoo.com (learner) wrote in comp.arch.embedded:> Hi, > I have a PCB that has a 512Kbits flash with Intel 386EXTC processor. > I am trying to test my PCB by hooking up the data and address lines on > logic analyzer and writing simple JMP (short) instruction in 386 > assembly language. I know that since my UCS is connected to CS of > Flash, processor will go to FFF0h address of Flash and execute the > instruction present at FFF0h. My Flash contains these simple > instructions: > > ADD Opcode > FFF0 EBh (opcode for short jump that takes 8 bit(here > 05h)dispalcement) > FFF1 05h > FFF2 00h > FFF3 00h > FFF4 00h > FFF5 00h > FFF6 EBh > FFF7 03h > > On logic analyzer, I should see FFF5 afetr FFF0/FFF1. Instead, all I > see is addresses being incremented sequentially with whatever data is > present on the different locations ie I see EB,05 etc on data bus but > processor is not executing the instructions. I have tried other > instructions too, like NOP and HLT but can't seem to make my processor > do what it is asked to do. Can some one suggest what the problem may > be and how can I fix it? > Thanks > > learnerOne of the first things I always used to do to check the memory bus on a new board was to jump the wait line active (or the ready line inactive), so I could stall the processor on the very first instruction fetch out of reset. On old Z80 designs, I could verify the MI, MREQ, and RD signals, and 0 on all the address lines, and also verify the binary pattern of the first instruction word on the data lines. That was always 0xF3 on my boards, because the first instruction in the code was always a DI, disable interrupts. Also note that on 32 bit x86 processors, the first instruction should be a far jump with 16-bit segment and 16-bit offset, because most of them actually set the internal segment base address to something strange. It should be a jump to F000:xxxx. -- Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://www.eskimo.com/~scs/C-faq/top.html comp.lang.c++ http://www.parashift.com/c++-faq-lite/ alt.comp.lang.learn.c-c++ http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.html
