Xilinx Virtex5 ILOGIC LOCations

Hi,

I have generated a DDR2 SDRAM interface with MIG2.0. It gave me a nice
project but I have to change the pin locations. After I make the
necessary changes I see that I have to tweak the ILOGIC, IODELAY
element locations also. They have location names like
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INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y302";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y302";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y300";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y300";
----------------------------------------------------------------------
in the ucf file. I have to change these locations appropriately
because otherwise I get routing problems.

Where can I find information about these locations? I searched
the .pdf files on the Xilinx website but couldn't find anything about
this. What does X0Y302 mean? Why X0Y302? ...

Thank you very much for your answers in advance.