FPGA tips - one for micro users

Tony Burch wrote:
> Hi all,
> I've just written a report called "Single Top FPGA Tips". May be of interest 
> for micro users who want to get started using FPGAs...
> http://www.burched.com/BurchED_Single_Top_Tips.pdf
> 
> I tried to think of the best tip that I could give to a microntroller 
> designer who has just started with FPGAs. That one is Single Top Tip #3. I 
> hope that is useful!
> Kind regards,
> Anthony Burch
> 
> 

As someone who's been doing FPGA design since the XC3000 was state of 
the ard, I like tip #6: Perform functional and Timing Simulation to 
verify the performance of your design.

I once had a client come to me in a panic because their customer 
expected a deliverable in a few days. My client had hired an old-timer 
with no FPGA experience to do the design. Their development cycle was:

1. Edit FPGA code
2. Place and route
3. Download and test code
4. Code no-workey. Back to step 1.
5. Repeat 1-4 until in panic mode.

When I asked about their simulation results, developer's response was, 
"We don't have time to simulate!"

Of course, my reply was, "No, you don't have time NOT to simulate."

After about a day of simulation, the problem was solved. Turned out to 
be a number of small things. The developer was a competent person and 
had written a fair amount of code.

Developing code without simulating is like writing software without a 
debugger. It can be done, but it takes longer and isn't near as much fun.

If, however, simulation is not employed, then the equivalent of the 
software development 'printf' statement is to connect appropriate 
internal signals to test points.

However, one has to be careful about that, as adding extra nodes to some 
nets can cause unexpected problems unless the synthesis tool settings 
are set correctly.

With Xilinx anyway, one can get a free license to use the ModelSim-XE 
simulator. For a beginning FPGA designer, this should be all that is 
needed. IIRC, there isn't a limit on the size of the design that can be 
simulated using the non-paid XE license. However, at certain circuit 
size points, the simulation S-L-O-W-S  W--A--Y  D---O---W---N