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Infineon TC1130 SDRAM controller.

Started by Unknown February 17, 2008
Hi,

We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro 
Mt48LC4M32B2).
Examining the memory signals with a logic analyser, the SDRAM is being 
correctly written, refreshed and read.
However, although we can see the expected data being output on a read 
command, the data does not reach the processor.

The SDRAM setup code that we are using on our own board has been run on the 
TC1130 evaluation board where it works satisfactorily.

Apart from the setup of the EBU registers as described in Infineon's App 
Note 32113, are there any other registers that affect the delivery
of bytes from the SDRAM to the LMB.

Thanks

Mike. 


On Feb 17, 10:00 pm, <mikedur...@totalise.co.uk> wrote:
> Hi, > > We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro > Mt48LC4M32B2). > Examining the memory signals with a logic analyser, the SDRAM is being > correctly written, refreshed and read. > However, although we can see the expected data being output on a read > command, the data does not reach the processor. > > The SDRAM setup code that we are using on our own board has been run on the > TC1130 evaluation board where it works satisfactorily. > > Apart from the setup of the EBU registers as described in Infineon's App > Note 32113, are there any other registers that affect the delivery > of bytes from the SDRAM to the LMB. > > Thanks > > Mike.
Hi Mike, As far as I'm aware this device may not be supported as it doesn't fit in the configuration table on page 14-104 of the user manual. Are you by any chance working with Lawrence Cuthbert at Siemens Protection Devices, as he recently sent me the same question? Best regards Richard
Yes, I'm suffering along with Lawrence.

We have established by use of a logic analyser that we are able to configure 
the SDRAM
controller to match the geometry of the SDRAM and correctly address banks, 
rows & columns,
but I do take your point about the configuration table in the user manual.

Please  consider the following, more detailed, description that I have
posted on the "Yahoo TASKINGforum" news group.

We have a TC1100 processor connected to a Micron MT48LC4M32B2 SDRAM.
The SDRAM has the following geometry :
4 Banks, 4096 rows(pages), 256 columns of 32bit words.

Using a logic analyser I can see data being written to the device and
correctly read from the device, however the read data does not reach
the LMB, that is it is neither visible to the Crossview debugger or
to the test application that we are running.

The same SDRAM/EBU controler initialisation code has been run on a
TC1130 TriBoard and apparently works; also the logic analyser traces
from the TriBoard match our board.

We are using the following startup sequence :-
EBU_CON = 0x0100000C0;

EBU_BUSCON0 = 0x30B20000; // SDRAM Type 0,
                                                      // 32 Bit,
                                                      // BC for SDRAM,
                                                      // Always access 
device.
EBU_ADDRSEL0 = 0xA8000031; // Address 0xA8000000 .. 0xA8FFFFFF,
EBU_BUSAP0 = 0x00070000;      // 7+1 cycles during burst access.

EBU_BUSCON1 = 0x30B20000;   // See EBU_BUSCON0
EBU_ADDRSEL1 = 0xA0000031; // Address 0xA0000000 .. 0xA0FFFFFF,
EBU_BUSAP1 = 0x00070000;       // 7+1 cycles during burst access.

EBU_SDRMCON0 = 0x20D31223;
EBU_SDRMOD0 = 0x00000023;  // CAS latency 2, Burst length 8
EBU_SDRMREF0 = 0x00000049; // Refresh every 9 * 64 clocks
                                                       // 1 additional
refresh command issued

// Initialise the following for completeness.
// Type 1 SDRAM not used.
EBU_SDRMCON1 = 0x20031223; // Always page & Bank miss.
EBU_SDRMOD1 = 0x00000023;
EBU_SDRMREF1 = 0x00000049;


Thanks for your time

Mike


<richard@rgledhill.com> wrote in message 
news:bccddf00-f9ae-483b-9afd-9a20d43d6462@n58g2000hsf.googlegroups.com...
> On Feb 17, 10:00 pm, <mikedur...@totalise.co.uk> wrote: >> Hi, >> >> We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro >> Mt48LC4M32B2). >> Examining the memory signals with a logic analyser, the SDRAM is being >> correctly written, refreshed and read. >> However, although we can see the expected data being output on a read >> command, the data does not reach the processor. >> >> The SDRAM setup code that we are using on our own board has been run on >> the >> TC1130 evaluation board where it works satisfactorily. >> >> Apart from the setup of the EBU registers as described in Infineon's App >> Note 32113, are there any other registers that affect the delivery >> of bytes from the SDRAM to the LMB. >> >> Thanks >> >> Mike. > > Hi Mike, > > As far as I'm aware this device may not be supported as it doesn't fit > in the configuration table on page 14-104 of the user manual. > > Are you by any chance working with Lawrence Cuthbert at Siemens > Protection Devices, as he recently sent me the same question? > > Best regards > Richard
mikedurham@totalise.co.uk wrote:
> > Yes, I'm suffering along with Lawrence.
Please do not top-post. Your answer belongs after (or intermixed with) the quoted material to which you reply, after snipping all irrelevant material. See the following links: -- <http://www.catb.org/~esr/faqs/smart-questions.html> <http://www.caliburn.nl/topposting.html> <http://www.netmeister.org/news/learn2quote.html> <http://cfaj.freeshell.org/google/> (taming google) <http://members.fortunecity.com/nnqweb/> (newusers) -- Posted via a free Usenet account from http://www.teranews.com

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