help with interrupt catching in Xilinx EDK 9.2 and custom IP

Dear all,
Here is my problem: I make a new microblaze project in EDK 9.2i and a
new custom IP with 1 register and 2 interrupts. I leave the default
settings everywhere, I link the interrupt to the xps_intc_0 "Intr"
port. I add:
	microblaze_enable_interrupts();
   {
      XStatus status;
      print("\r\nRegistering TEST_INT_Intr_DefaultHandler() to
xps_intc_0...\r\n");
		 status = XIntc_Connect(&intc,
XPAR_XPS_INTC_0_TEST_INT_0_IP2INTC_IRPT_INTR,
						(XInterruptHandler)TEST_INT_Intr_DefaultHandler,
						XPAR_TEST_INT_0_BASEADDR);
		 /* Enable the interrupt vector at the interrupt controller */
		 XIntc_Enable(&intc, XPAR_XPS_INTC_0_TEST_INT_0_IP2INTC_IRPT_INTR);
	   TEST_INT_EnableInterrupt(XPAR_TEST_INT_0_BASEADDR);
      if (status == 0) {
         print("TEST_INT_Intr_DefaultHandler registration PASSED\r
\n");
      }
      else {
         print("TEST_INT_Intr_DefaultHandler registration FAILED\r
\n");
      }
   }
while(1)
;

This basically enable the newly created "test_int" device interrupt
and links this interrupt to the interrupt controller intc. "test_int"
has a counter and triggers an interrupt every 4 secs (ie.
IP2Bus_IntrEvent <= ('1','1'); evey 4 sec and IP2Bus_IntrEvent <=
('0','0'); otherwise).

Actually, TEST_INT_Intr_DefaultHandler() is called avery 4 sec as
expected but the DISR value it reads is: 0x00000000. I would have
expected it to end by '11000' (DEV_LVL_IS='11') as the two interrupts
are called at the same time.

Do you have any clue?
Thanks in advance,
Laurent.