On Tue, 29 Apr 2008 13:09:56 -0500, Grant Edwards <grante@visi.com> wrote:>On 2008-04-29, Paul Keinanen <keinanen@sci.fi> wrote: >> On Tue, 29 Apr 2008 00:07:01 -0400, Robert Adsett >><sub2@aeolusdevelopment.com> wrote: >> >> >>>I vaguely remember seeing a protocol that exhibited both little and big >>>endian elements but that may simply be "an undigested piece of meat". >> >> I have seen Modbus implementations, in which the 16 bit registers are >> (by definition) big endian, but when trying to represent 32 bit >> integers or 32 bit floating point values, the least significant part >> is in the lower register. > >IIRC, 32-bit values on the PDP-11 were traditionally handled >that way: the word order was different than the byte order >within the words.While the PDP-11 was little endian, the 32 bit operand for MUL, DIV and ASHC instructions had the most significant part in R0 (or R2 or R4) and the least significant 16 bit value in R1 (or R3 or R5), so in a sense the "wrong" way around. However, no 32 move instructions existed, so you had to move R0 and R1 with two separate MOV instructions from/to memory, so it was up to the compiler or assembler programmer into which order the registers were loaded in memory. However, the PDP-11/VAX floating point format looks strange in memory. The first 16 bit word contained the sign, exponent and the most significant part of mantissa and the following word(s) contained the less significant part(s) of the mantissa. In the first 16 bit word, the sign was at the leftmost portion, followed by the 8 bit exponent and 7 bit of the mantissa at the right end. When storing a 32 bit float in memory and viewing it by sequential byte addresses, the first byte contained the last bit of exponent, the 7 most significant part of mantissa. The second byte contained the sign and 7 most significant part of exponent. The third byte contained the least significant bits of the mantissa and the 4th byte the middle bits from the mantissa. Paul
Floating point numbers and endian ness??
Started by ●April 25, 2008
Reply by ●April 30, 20082008-04-30
Reply by ●April 30, 20082008-04-30
On 2008-04-30, Paul Keinanen <keinanen@sci.fi> wrote:>>IIRC, 32-bit values on the PDP-11 were traditionally handled >>that way: the word order was different than the byte order >>within the words. > > While the PDP-11 was little endian, the 32 bit operand for MUL, DIV > and ASHC instructions had the most significant part in R0 (or R2 or > R4) and the least significant 16 bit value in R1 (or R3 or R5), so in > a sense the "wrong" way around. However, no 32 move instructions > existed, so you had to move R0 and R1 with two separate MOV > instructions from/to memory, so it was up to the compiler or assembler > programmer into which order the registers were loaded in memory.Right, and my foggy recollection was that the convention was to store the most significant word at <addr> and the least significant word at <addr+2>. I wouldn't be surprised if I've conflated the 32-bit integer layout with the (odd, IMO) floating point layout you described. -- Grant Edwards grante Yow! I'm changing the at CHANNEL ... But all I get visi.com is commercials for "RONCO MIRACLE BAMBOO STEAMERS"!
