embedded processor with large memory support

tns1 wrote:
> Paul Keinanen wrote:
>> On Wed, 13 Aug 2008 11:44:43 -0700, tns1 <tns1@cox.net> wrote:
> ...
>> If you already require a 32 bit integer processor, are you sure you
>> need HW floating point ?
>>
>> With 32 bit integer hardware single precision multiplication/division
>> is quite trivial (unless you need full IEEE compliance :-).
>>
> The existing system uses a HW FPU, so its just easier to require this on 
> the new system rather than do the up-front analysis to justify using a 
> SW solution. As long as it could do basic single precision operations 
> and was IEEE754 compliant I suspect it would be OK. Like so many 
> projects I need to architect a general solution before all the details 
> are known.

Any decent 'C' compiler on an embedded processor gives a good emulation 
of single and double precision floating points operations. Most of these 
are IEEE754 compliant (as opposed to many HW implementations which are not).

The only advantage of a HW implementation is speed. If the SW one is 
fast enough on the processor you have selected then there is no need 
whatsoever for the HW.

Michael Chapman wrote:
> tns1 wrote:
>> Paul Keinanen wrote:
>>> On Wed, 13 Aug 2008 11:44:43 -0700, tns1 <tns1@cox.net> wrote:
>> ...
>>> If you already require a 32 bit integer processor, are you sure you
>>> need HW floating point ?
>>>
>>> With 32 bit integer hardware single precision multiplication/division
>>> is quite trivial (unless you need full IEEE compliance :-).
>>>
>> The existing system uses a HW FPU, so its just easier to require this 
>> on the new system rather than do the up-front analysis to justify 
>> using a SW solution. As long as it could do basic single precision 
>> operations and was IEEE754 compliant I suspect it would be OK. Like so 
>> many projects I need to architect a general solution before all the 
>> details are known.
> 
> Any decent 'C' compiler on an embedded processor gives a good emulation 
> of single and double precision floating points operations. Most of these 
> are IEEE754 compliant (as opposed to many HW implementations which are 
> not).
> 

Most decent compilers (and libraries) will give you a choice of 
compliant behaviour or non-compliant but smaller and faster behaviour. 
They also (except perhaps for small cpus which are wholly unsuited for 
complex maths) normally implement both singles and doubles, and 
sometimes long doubles - hardware implementations are often limited to 
single precision.

> The only advantage of a HW implementation is speed. If the SW one is 
> fast enough on the processor you have selected then there is no need 
> whatsoever for the HW.
> 

I think hardware floating point can make sense on specialised devices, 
such as floating point DSPs.  But for general usage, there are few 
advantages and many disadvantages until you are talking about much 
larger cpu devices such as x86 or PPC architectures.

In article <tfc6a499gladgnnb9a4adimofqbbtml6qo@4ax.com>,
Paul Keinanen  <keinanen@sci.fi> wrote:
>Float add/sub are a bit more costly due to the normalization and
>demoralization required,

You know, I'd always suspected that demoralization was a requirement of
floating-point support...


-- 
   Wim Lewis <wiml@hhhh.org>, Seattle, WA, USA. PGP keyID 27F772C1