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Hi Dries Dries Driessens wrote: > > >I'm not saying people should buy the latest of the latest. For example: >last year I did my thesis on a complex FPGA design. >I worked on a AMD K5-2 266MHz portable with just 96MB SoDIMM, running on >Windows 98 SE. >Synplify & Quartus worked perfect on my machine. I had to wait 2 times >longer than on a 1GHz machine, but it worked perfectly. I have 256MB on the Duron which seems to be fine and 128MB on the Pentium 1.. >I can advise to people on low-budget to synthesise your design not on >ISE Webpack or Quartus Web Edition, but to use the free EDA-tools >Leonardo Spectrum-Altera edition or Xilinx edition. As always these >tools are limited, but they preform the synthesis task about 600% beter >than ISE or Quartus! Afterwards you still have to place & route your >design in ISE or Quartus of course... Sounds good, but there must be a catch. Is there a limit to the size of the files you can synthesise ? Leonardo Spectrum can't be making much money giving their software away. Xilinx and Altera I can understand, as they stand to sell more FPGAs and get more people designing with them. It must also be dependant on the way you write your VHDL code surely. >If you still want to improve your performance, buy some more memory. >Synthesis and place & route require lots of memory! If the design gets >too large, your pc starts swapping on his disk. In comparison: a >harddisk has a seek time of about 7 ms, memory 70 ns or less. This means >that when you start swapping, you are slowed about a 100 000 times! Even >if it is only 1000 times, your 1s synthesis with memory will last 18 >minutes!!! > >Also if your pc crashes a lot, my experience that this may be caused by >too less memory or low-end processors (Duron/Celeron/C3). No, I don't have too many problems with the Duron crashing. The synthesis problems on the 6809 core seemed to go away when I upgraded the web pack software to 4.2. I can only summise the file was too big for the synthesis tools. One thing I might comment on, the Green Mountain (?) 68HC11 design would not fit into a 200K gate Xilinx FPGA when I tried to compile it with the web pack software, in fact it was 200% over the capacity of the FPGA. What sort of job does Leonado Spectrum do on it ? Has anyone tried synthesising the 68hc11 core on other synthesis tools ? I think I read somewhere it was pretty much designed for the Green Mountain VHDL compiler. I managed to get my 68HC11 into the XC2S200 quite easily. And that included a UART, DAT RAM (dynamic Address translation), parallel I/O port and 1KByte ROM. The 68HC11 works fine with a stightly modified 6800 monitor program (SWTBUG) (The stack was adjusted for the Y index register). I made a post on a competeing mailing list a little while back about the divide instructions. The 68HC11 manual says IDIV and FDIV work in 41 clock cycles. Using the 16 bit ALU I have two shift cycles and one subtract cycle X 16 bits which makes 48 cycles plus instruction decode and register shuffling. I figure I can get it down to 32 cycles + by performing the two register shifts outside the ALU, that is assuming I have interpreted the operation of the divide correctly. I have not looked at the Green Mountains design in detail, and I'm not even sure if it is a complete implementation. I think they might have done the interrupts a little differently. Optimizing the divide instructions and sorting out the condition codes for them is pretty much the last thing I need to do for my 68hc11 design. John. -- http://members.optushome.com.au/jekent |
68hc11 (was Installing Qauartus)
Started by ●February 6, 2003
