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What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor? |
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What are peoples opinion of the Altera Nios Processor?
Started by ●March 17, 2003
Reply by ●March 18, 20032003-03-18
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We have tried NIOS ver 1.0 ON WIN98. ver 1.0 was horrible with win98, informed ALTERA application engineers, but not succussful. Altera requested to upgrade to MSWIN2000 with NIOS update version. The new version is fine and we are happy with it. Since the is not responding, we have to get clarifications in debugging c routines. b.kannaiah --- wrote: > What kind of problems have you experienced? How was > there support? > If you could do it again would you use the NIOS > processor? > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > > ">http://docs.yahoo.com/info/terms/ ________________________________________________________________________ Missed your favourite TV serial last night? Try the new, Yahoo! TV. visit http://in.tv.yahoo.com |
Reply by ●March 18, 20032003-03-18
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barrem23 wrote: >What kind of problems have you experienced? > We had one problem with the VHDL-synthesis-flow. After synthesis with Synplify, we couldn't place & route with Quartus. That was because SOPC Builder generated low-level stuff in the VHDL specifically for your component. The solution was selecting FLEX components in SOPC Builder. >How was there support? > An FAE from France helped us out. >If you could do it again would you use the NIOS processor? > All depends. If you want high performance, choose a seperate processor-IC. If you have a complex FPGA design, and you have some room left on your FPGA, choose Nios, Microblaze, Leon Sparc of OpenRisc. If you're developing a high-volume ASIC. Choose Leon Sparc or OpenRisc. If you're developing a mid-volume ASIC. Choose Nios or Microblaze on Cyclone/Spartan or Hardcopy devices. Maybe even the next generation gate array from Nec or LSI with a Leon Sparc or OpenRisc. If you're developing a low-volume ASIC, you live in the past ;-) >To post a message, send it to: >To unsubscribe, send a blank message to: > >">http://docs.yahoo.com/info/terms/ > >. > |
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Reply by ●March 18, 20032003-03-18
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Oooh... good topic for me (and in light of recent list politics, I sure
hope it's interesting to some of you as well :) ) I'll be writing a paper in the next few weeks: a survey of commercially and freely available 32-bit RISC IP cores. For the paper, I'm interested in hard and soft cores, but for the future, my research will require one that I can customize (that is, VHDL or Verilog available). I'm already looking at LEON for that... but I'd appreciate input as well. Thanks Josh Pfrimmer, B.Eng _____ University of Victoria <mailto:> -----Original Message----- From: Dries Driessens [mailto:] Sent: March 17, 2003 11:46 PM To: Subject: Re: [fpga-cpu] What are peoples opinion of the Altera Nios Processor? We had one problem with the VHDL-synthesis-flow. After synthesis with Synplify, we couldn't place & route with Quartus. That was because SOPC Builder generated low-level stuff in the VHDL specifically for your component. The solution was selecting FLEX components in SOPC Builder. >How was there support? > An FAE from France helped us out. >If you could do it again would you use the NIOS processor? > All depends. If you want high performance, choose a seperate processor-IC. If you have a complex FPGA design, and you have some room left on your FPGA, choose Nios, Microblaze, Leon Sparc of OpenRisc. If you're developing a high-volume ASIC. Choose Leon Sparc or OpenRisc. If you're developing a mid-volume ASIC. Choose Nios or Microblaze on Cyclone/Spartan or Hardcopy devices. Maybe even the next generation gate array from Nec or LSI with a Leon Sparc or OpenRisc. If you're developing a low-volume ASIC, you live in the past ;-) |
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Reply by ●March 18, 20032003-03-18
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> I'll be writing a paper in the next few weeks: a survey of
commercially and > freely available 32-bit RISC IP cores. Interssting. You may post a link to the paper to this group, when it is ready. > For the paper, I'm interested in hard and soft cores, but for the future, > my research will require one that I can customize (that is, VHDL or Verilog > available). I'm already looking at LEON for that... but I'd appreciate > input as well. We used LEON in some project, about a year ago. From the functional point LEON was ok, it worked well. The good point is, that LEON comes with a compiler/assembler toolchain that works out-of-the-box. The drawback of LEON on FPGAs is that it is quite large and pretty slow. We have synthesized LEON for a Xilinx Virtex XCV800-5, the maximum speed we could reach was about 25 MHz, the design used 3800 slices. I guess, we could have pushed this somewhat further by floorplanning, but 25 MHz was sufficient performance for our application. Compared to Microblaze, LEON is much larger and slower, but comparing them is not really fair, as Microblaze was specifically optimized for Virtex FPGAs. Best regards, Christian -- Christian Plessl <> Computer Engineering Lab (TIK), ETH Zurich, Switzerland |
Reply by ●March 18, 20032003-03-18
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> > I'll be writing a paper in the next few weeks: a survey of
commercially and > > freely available 32-bit RISC IP cores. > > Interssting. You may post a link to the paper to this group, when it is ready. > > > For the paper, I'm interested in hard and soft cores, but for the future, > > my research will require one that I can customize (that is, VHDL or Verilog > > available). I'm already looking at LEON for that... but I'd appreciate > > input as well. > > We used LEON in some project, about a year ago. From the functional point LEON > was ok, it worked well. The good point is, that LEON comes with a > compiler/assembler toolchain that works out-of-the-box. The drawback of LEON > on FPGAs is that it is quite large and pretty slow. We have synthesized LEON > for a Xilinx Virtex XCV800-5, the maximum speed we could reach was about 25 > MHz, the design used 3800 slices. I guess, we could have pushed this > somewhat further by floorplanning, but 25 MHz was sufficient performance for > our application. Compared to Microblaze, LEON is much larger and slower, but > comparing them is not really fair, as Microblaze was specifically optimized > for Virtex FPGAs. > A Java Processor is not a classical RISC processor, but as in my implementation it is a simple stack machine with a very small instruction set (reduced instruction set :-). It has 47 different instrcutions, all variations counted. So instructions can be coded in 8 bit WITH some operand. And it fits in an Altera ACEX 1K50, about 2000 LCs (depends on the periphery you use) and runns at about 30 MHz in the slowest speed grade. Did port it two weeks ago to Cyclone (yes a porting was necessary because of the different embedded memory), and Quartus says it should run at about 80 MHz. Interested? Martin Schoeberl |
