Use for 2 bit opcode ?
Started by ●April 2, 2005
Can anyone think of a use for a two bit opcode ?
It all started when I decided to use a 42 bit code. Three opcodes are
packed into 128 bits, but that leaves 2 bits left over, so what can I
do with them ?
Reply by ●April 2, 20052005-04-02
--- In fpga-cpu@fpga..., "Rob Finch" <robfinch@s...> wrote:
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes
are
> packed into 128 bits, but that leaves 2 bits left over, so what can
I
> do with them ?
Sure, there are at least two things I could suggest. One is to use
them as if they were full opcodes but with the remaining 40 bits fixed
at 0 or some other value. Or you can pick your three most commonly
used opcodes (along with NOP) and map them to those. This will let
you pack 4 instructions in the 128 bit word in those cases.
Reply by ●April 2, 20052005-04-02
----- Original Message -----
From: "Rob Finch" <robfinch@robf...>
To: <fpga-cpu@fpga...>
Sent: Saturday, April 02, 2005 8:47 PM
Subject: [fpga-cpu] Use for 2 bit opcode ? >
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes are
> packed into 128 bits, but that leaves 2 bits left over, so what can I
> do with them ?
Lisp machines had tag bits, perhaps you can use them for something similar.
Leon
From: "Rob Finch" <robfinch@robf...>
To: <fpga-cpu@fpga...>
Sent: Saturday, April 02, 2005 8:47 PM
Subject: [fpga-cpu] Use for 2 bit opcode ? >
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes are
> packed into 128 bits, but that leaves 2 bits left over, so what can I
> do with them ?
Lisp machines had tag bits, perhaps you can use them for something similar.
Leon
Reply by ●April 2, 20052005-04-02
Leon Heller wrote:
>>Can anyone think of a use for a two bit opcode ?
>>
>>It all started when I decided to use a 42 bit code. Three opcodes are
>>packed into 128 bits, but that leaves 2 bits left over, so what can I
>>do with them ?
>>
>>
>
>Lisp machines had tag bits, perhaps you can use them for something similar.
>
>Leon >
But this is opcodes ... My guess could be a return instruction ... 0 no
return 1 return after instruction #1
2 return after instruction #2 3 return after instruction #3
>>Can anyone think of a use for a two bit opcode ?
>>
>>It all started when I decided to use a 42 bit code. Three opcodes are
>>packed into 128 bits, but that leaves 2 bits left over, so what can I
>>do with them ?
>>
>>
>
>Lisp machines had tag bits, perhaps you can use them for something similar.
>
>Leon >
But this is opcodes ... My guess could be a return instruction ... 0 no
return 1 return after instruction #1
2 return after instruction #2 3 return after instruction #3
Reply by ●April 2, 20052005-04-02
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, but that leaves 2 bits left over, so what can I
>do with them ? Some ideas:
-Two flags for conditional execution
(Bit 0 says execute instruction 0 and 1 in this word only if the last
comparison was successfull, the other bit says the same for the
remaining instruction)
-large immediates
If the bit 0 is set the opcode for instruction 2 in the word becomes a
32-bit immediate for the first operand of instruction 0
-flag to switch virtual register files
You have two sets of register files. One set supplies source operands
and the other one is only used as destination operands.
Whenever the bit is set role of the two are switched. This guarantees
that all instructions with the same bit value can be executed in any
order or in parallel. This is a nice way to have an abstract ISA for
VLIW where you do not know the number of instruction units in advance.
- flag whether there is a branch delay slot
Have fun,
Kolja Sulimma
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, but that leaves 2 bits left over, so what can I
>do with them ? Some ideas:
-Two flags for conditional execution
(Bit 0 says execute instruction 0 and 1 in this word only if the last
comparison was successfull, the other bit says the same for the
remaining instruction)
-large immediates
If the bit 0 is set the opcode for instruction 2 in the word becomes a
32-bit immediate for the first operand of instruction 0
-flag to switch virtual register files
You have two sets of register files. One set supplies source operands
and the other one is only used as destination operands.
Whenever the bit is set role of the two are switched. This guarantees
that all instructions with the same bit value can be executed in any
order or in parallel. This is a nice way to have an abstract ISA for
VLIW where you do not know the number of instruction units in advance.
- flag whether there is a branch delay slot
Have fun,
Kolja Sulimma
Reply by ●April 2, 20052005-04-02
> -large immediates
> If the bit 0 is set the opcode for instruction 2 in the word becomes
a
> 32-bit immediate for the first operand of instruction 0
>
I like the large immediate idea. If I flag a whole opcode field as an
immediate, then I can squeeze 64 bit immediates into only two opcodes.
>
> Have fun,
>
Something I ran into today: why aren't branch displacements a
combination of both relative and absolute addressing ? The high order
bits of the displacement could be used as a relative offset to a block
of instructions, while the low order bits are used as an absolute
index. I'm thinking it would be handy to get rid of pc displacement
adder bits. It might be useful when the size of the design is
important. It would speed up the displacement adder as well. The low
order bits could just be passed directly through to the pc. With a
typical sixteen bit displacement, the low order twelve bits could be
passed along verbatium as a page index, while the high order four bits
select a block -8 to +7 blocks away.
Reply by ●April 2, 20052005-04-02
Rob Finch wrote:
>
> Something I ran into today: why aren't branch displacements a
> combination of both relative and absolute addressing ? The high order
> bits of the displacement could be used as a relative offset to a block
> of instructions, while the low order bits are used as an absolute
> index. I'm thinking it would be handy to get rid of pc displacement
> adder bits. It might be useful when the size of the design is
> important. It would speed up the displacement adder as well. The low
> order bits could just be passed directly through to the pc. With a
> typical sixteen bit displacement, the low order twelve bits could be
> passed along verbatium as a page index, while the high order four bits
> select a block -8 to +7 blocks away.
>
Nice idea, just remember your code will relocate to 4k boundrys.
Ben alias woodelf
>
> Something I ran into today: why aren't branch displacements a
> combination of both relative and absolute addressing ? The high order
> bits of the displacement could be used as a relative offset to a block
> of instructions, while the low order bits are used as an absolute
> index. I'm thinking it would be handy to get rid of pc displacement
> adder bits. It might be useful when the size of the design is
> important. It would speed up the displacement adder as well. The low
> order bits could just be passed directly through to the pc. With a
> typical sixteen bit displacement, the low order twelve bits could be
> passed along verbatium as a page index, while the high order four bits
> select a block -8 to +7 blocks away.
>
Nice idea, just remember your code will relocate to 4k boundrys.
Ben alias woodelf
Reply by ●April 3, 20052005-04-03
Has there been any work done on FPGA Chess computers ?
I thought building an FPGA machine that generated a ply tree
would be pretty easy to do. The trick may be in working out
the best position analysis and evaluation strategy.
I remember many years ago seeing a hardwired chess computer,
in the newspaper. I'm not sure if if used FPGAs or not.
Did Deep Blue use FPGAs ?
John.
--
http://members.optushome.com.au/jekent
I thought building an FPGA machine that generated a ply tree
would be pretty easy to do. The trick may be in working out
the best position analysis and evaluation strategy.
I remember many years ago seeing a hardwired chess computer,
in the newspaper. I'm not sure if if used FPGAs or not.
Did Deep Blue use FPGAs ?
John.
--
http://members.optushome.com.au/jekent
Reply by ●April 3, 20052005-04-03
John Kent wrote:
>Has there been any work done on FPGA Chess computers ? >
Yes.
http://www.hydrachess.com/
>Did Deep Blue use FPGAs ? No, ASICs
Kolja Sulimma
>Has there been any work done on FPGA Chess computers ? >
Yes.
http://www.hydrachess.com/
>Did Deep Blue use FPGAs ? No, ASICs
Kolja Sulimma
Reply by ●April 4, 20052005-04-04
Hi Kolja
Looks interesting.
One of the first projects I was interested in when I bought my 6800 D2 kit
back in the late 70s was converting Sargon from the Z80 to the 6800.
Dan and Kathe Spracklen released a book with the source code called
"Sargon: a Computer Chess Program"
http://www.answers.com/topic/sargon-chess
At the time we were using a 300baud Kansas City Standard tape loader.
We got so far coding it that my brother thought he'd throw away the source
and patch the binary ... BIG mistake !. He/we never did finish the project.
We got the game to make an opening move on the memory mapped VDU,
then BLAT, the opposition move scambled it's piece on the display.
Not good :-)
The Byte Book of Pascal had a chess program in it (am I showing my age?)
which was a tinsy bit to big for my 8 bit machine and the Lucidata Pcode
Pascal
compiler at the time.
I guess these days you have gnu chess, although I'd hate to try and
implement
that in hardware.
Anyway I have the Sargon source code book somewhere. I'm not sure if it is
possible to microcode a move generator that will go through all possible
movements
of a chess piece. Each move could be stored in a 12 x 12 nybble array
(8 x 8 with a 2 nybble perimeter to test for out of bounds moves).
I think that was how Sargon was implemented.
Empty, Pawn, Rook, Knight, Bishop, Queen, King and Boundary could be
code in 3 bits
and one bit for the side (white / black)
With 256K bytes of RAM, that would allow 3640 moves to be stored.
My guess is that hydrachess is a parallel archictecture which just farms
off more
moves in each of the processors.
Evaluation of a position would take into account which pieces were being
attacked
which pieces were attacking, how many peices were defending other peices and
how many squares the peices controlled. Also if you where in check !
The end game probably demands another strategy ... how to get the
opponent in check mate. Maybe that comes out in the wash, by virtue of
the squares being controlled.
Just a few thoughts to fill up peoples mailboxes :-)
John.
Kolja Sulimma wrote:
>John Kent wrote: >
>>Has there been any work done on FPGA Chess computers ?
>>
>>
>>
>>
>>
>Yes.
>http://www.hydrachess.com/ >
>>Did Deep Blue use FPGAs ?
>>
>>
>>
>>
>No, ASICs
>
>Kolja Sulimma --
http://members.optushome.com.au/jekent
Looks interesting.
One of the first projects I was interested in when I bought my 6800 D2 kit
back in the late 70s was converting Sargon from the Z80 to the 6800.
Dan and Kathe Spracklen released a book with the source code called
"Sargon: a Computer Chess Program"
http://www.answers.com/topic/sargon-chess
At the time we were using a 300baud Kansas City Standard tape loader.
We got so far coding it that my brother thought he'd throw away the source
and patch the binary ... BIG mistake !. He/we never did finish the project.
We got the game to make an opening move on the memory mapped VDU,
then BLAT, the opposition move scambled it's piece on the display.
Not good :-)
The Byte Book of Pascal had a chess program in it (am I showing my age?)
which was a tinsy bit to big for my 8 bit machine and the Lucidata Pcode
Pascal
compiler at the time.
I guess these days you have gnu chess, although I'd hate to try and
implement
that in hardware.
Anyway I have the Sargon source code book somewhere. I'm not sure if it is
possible to microcode a move generator that will go through all possible
movements
of a chess piece. Each move could be stored in a 12 x 12 nybble array
(8 x 8 with a 2 nybble perimeter to test for out of bounds moves).
I think that was how Sargon was implemented.
Empty, Pawn, Rook, Knight, Bishop, Queen, King and Boundary could be
code in 3 bits
and one bit for the side (white / black)
With 256K bytes of RAM, that would allow 3640 moves to be stored.
My guess is that hydrachess is a parallel archictecture which just farms
off more
moves in each of the processors.
Evaluation of a position would take into account which pieces were being
attacked
which pieces were attacking, how many peices were defending other peices and
how many squares the peices controlled. Also if you where in check !
The end game probably demands another strategy ... how to get the
opponent in check mate. Maybe that comes out in the wash, by virtue of
the squares being controlled.
Just a few thoughts to fill up peoples mailboxes :-)
John.
Kolja Sulimma wrote:
>John Kent wrote: >
>>Has there been any work done on FPGA Chess computers ?
>>
>>
>>
>>
>>
>Yes.
>http://www.hydrachess.com/ >
>>Did Deep Blue use FPGAs ?
>>
>>
>>
>>
>No, ASICs
>
>Kolja Sulimma --
http://members.optushome.com.au/jekent
