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Hi all
Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ?
Best
bobi
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How many MIPS can the lpc2106 do ?
Started by ●December 2, 2003
Reply by ●December 2, 20032003-12-02
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----- Original Message ----- From: "bobi catorski" <> To: <> Sent: Tuesday, December 02, 2003 7:28 AM Subject: [lpc2100] How many MIPS can the lpc2106 do ? > Hi all > > Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ? Philips claims 54 Dhrystone MIPS at 60 MHz: http://www.semiconductors.philips.com/acrobat/literature/9397/75011962.pdf Leon |
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Reply by ●January 9, 20042004-01-09
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--- In , "Leon Heller" <leon_heller@h...> wrote: > > Hi all > > > > Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ? > > Philips claims 54 Dhrystone MIPS at 60 MHz: http://www.semiconductors.philips.com/acrobat/literature/9397/75011962 > > Leon This is an ideal theoretical number using Dhrystone. Has any one done some real world benchmarking? How effective is the flash "cache" with real code? |
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Reply by ●January 13, 20042004-01-13
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Hi Ken, we did some measurements of code ranging from mostly linear execution (best case) to pretty much jump tables with very little linear code (worst case). If the code is mostly linear (let's assume one branch every 20 instructions or less), execution from RAM and execution from Flash were virtually identical, 99+% performance from Flash. In particular loops that are not nested do not cause wait states. This might not be realistic for larger programs but it could be close to a small DSP control loop. Code with lots of branches and no loops was slower by approx. 10-15% running from Flash compared to running from RAM. Unfortunately I can not provide the programs used, they are part of a benchmark suite that needs a license. This second program is designed to show performance without cache (it is called cache-buster ;-). IMHO it is not very close to realistic code and generates performance numbers worse than average code. Realisticly, we see operation from Flash (@ 60 MHz) approx. 95% of the performance compared to running from RAM. This looks extremely good to us and the claimed "0-waitstate execution" can pretty much be confirmed. It is much closer to 0 waitstates than to 1 waitstates, let's call it a rounding error. Cheers, Bob --- In , "kendwyer" <kendwyer@y...> wrote: > --- In , "Leon Heller" <leon_heller@h...> > wrote: > > > Hi all > > > > > > Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ? > > > > Philips claims 54 Dhrystone MIPS at 60 MHz: > > > > > http://www.semiconductors.philips.com/acrobat/literature/9397/75011962 > > > > Leon > > This is an ideal theoretical number using Dhrystone. Has any one done > some real world benchmarking? How effective is the flash "cache" with > real code? |
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Reply by ●January 13, 20042004-01-13
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Thanks Bob, I assume you had the MAM fully enable and MAMTIM set to 0x3 for your 60MHz tests? Ken --- In , "lpc2100_fan" <lpc2100_fan@y...> wrote: > Hi Ken, > > we did some measurements of code ranging from mostly linear execution > (best case) to pretty much jump tables with very little linear code > (worst case). If the code is mostly linear (let's assume one branch > every 20 instructions or less), execution from RAM and execution from > Flash were virtually identical, 99+% performance from Flash. In > particular loops that are not nested do not cause wait states. This > might not be realistic for larger programs but it could be close to a > small DSP control loop. > > Code with lots of branches and no loops was slower by approx. 10-15% > running from Flash compared to running from RAM. Unfortunately I can > not provide the programs used, they are part of a benchmark suite that > needs a license. This second program is designed to show performance > without cache (it is called cache-buster ;-). IMHO it is not very > close to realistic code and generates performance numbers worse than > average code. > > Realisticly, we see operation from Flash (@ 60 MHz) approx. 95% of the > performance compared to running from RAM. This looks extremely good to > us and the claimed "0-waitstate execution" can pretty much be > confirmed. It is much closer to 0 waitstates than to 1 waitstates, > let's call it a rounding error. > > Cheers, Bob > > --- In , "kendwyer" <kendwyer@y...> wrote: > > --- In , "Leon Heller" <leon_heller@h...> > > wrote: > > > > Hi all > > > > > > > > Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ? > > > > > > Philips claims 54 Dhrystone MIPS at 60 MHz: > > > > > > > > http://www.semiconductors.philips.com/acrobat/literature/9397/75011962 > > > > > > Leon > > > > This is an ideal theoretical number using Dhrystone. Has any one done > > some real world benchmarking? How effective is the flash "cache" with > > real code? |
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Reply by ●January 13, 20042004-01-13
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Ken, MAM fully enabled but we altered the sourcecode several times and I can not remember whether we had set MAMTIM to 3 or to 2 (which did work). I got the information about MAMTIM later in the game. According to the information I have MAMTIM needs to be set 3 or even 4 (in case we would potentially exceed max. So, I honestly could not tell whether it was 2 or 3. It does make a difference of a few (single digit) percentage points, I know. Calculating for worst case please assume it was done with MAMTIM=2. For us the performance is plenty and a lot higher compared to devices that either work from external Flash, have a narrow internal bus or like Atmel's 55800 devices execute from an internal/external Flash (Multi-Chip-Module), sitting in the same package but executing like an external memory. Cheers, Bob --- In , "kendwyer" <kendwyer@y...> wrote: > Thanks Bob, > > I assume you had the MAM fully enable and MAMTIM set to 0x3 for your > 60MHz tests? > > Ken > |
