--- In l..., "derbaier" wrote:
>
> --- In l..., "jayasooriah" wrote:
> >
> > A feature of LPC's innovative design is the use of one a register to
> > limit amount RAM and ROM enabled. This is done in the supplied boot
> > loader and this is the real reason for keeping boot loader internals
> > secret.
> > That is an interesting allegation to make without any proof. The
> reasons stated by Phillips make more sense.

To my knowledge Philips has never made any statement about this.

All Philips has to do is to document bits of the special register at
0x3fff8000. Philips has not and the most compelling reason for this
is as I explained.

You are probably referring to speculation on the part of some forum
readers who appear not conversant with the exact what mechanism used
in the LPC to limit FLASH and RAM sizes.

Anyone can establish the truth (or otherwise) of the "allegation" by a
simple experiment. I have had independent confirmation of my findings
from those who bothered to do the experiment.

> There is no "innovative
> design" involved in mapping out defective RAM and FLASH since it has
> to be done by some method or other in all silicon designs that
> incorporate RAM and FLASH. Silicon defects are fairly randomly
> distributed, but since memory occupies such a larg die area memory is
> more freqeuntly hit by defects. It makes more economic sense to simply
> map out the defects rather than discarding the whole die. Otherwise we
> would all be paying higher prices for parts that were simply good/bad
> binned.

The "innovation" I was referring to relates to the LPC project itself.



My understanding is that the LPC is the product of an initiative to
redesign everything ground up (RAM, FLASH, CACHE UART, TIMERS, etc) so
as to produce a design that is cost effective.

Each component had to be made simpler and the designers did this by
cutting down transistors. The result is what we see -- rather unusual
bugs. Those of us in systems design classify bugs as "design" or
"implementation" and in the case of LPC, a large portion appear to be
in the "design" basket.

I am quite sure the recent discovery by another poster that SRAM on
LPC is really pseudo static dynamic RAM is not the last we will hear
of what is in the LPC family of processors.



If you worked out the bits in the register I referred to above that
controlled FLASH and RAM size, you cannot but conclude that it has not
to do with mapping out defective RAM or ROM cells.

> > If they released this information anyone could "upgrade" their part to
> > the full silicon capabilities without limits imposed by Philips "boot
> > loader".
>
> That is your allegation.

Philips can prove this "allegation" false. It has not.

> For a hobbiest, it might even be worth
> getting the capabilities that were not paid for. However, it is very
> likely that the mapped out memory has failed some corner cases during
> pre or post packaging testing, so it would make very little sense for
> a commercial project to "upgrade" parts by such methods.

This makes sense if register at 0x3fff8000 does what you think it
does. A simple experiment will demonstrate this is not the case.

>
> --Dave
>

Jaya

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--- In l..., "jayasooriah"
wrote:
> My understanding is that the LPC is the product of an initiative to
> redesign everything ground up (RAM, FLASH, CACHE UART, TIMERS,
etc) so
> as to produce a design that is cost effective.
>
> Each component had to be made simpler and the designers did this by
> cutting down transistors.

Do you have any information to back this assertion, or is it pure
speculation? It does not match my understanding of the origin of the
design.

> > > If they released this information anyone could "upgrade" their
part to
> > > the full silicon capabilities without limits imposed by
Philips "boot
> > > loader".

Do you have any information to back the assertion that such
an "upgrade" is possible, or is it pure speculation? It does not
match my understanding what is possible. As others have pointed out,
even if it were possible, it would be a very bad idea to use such an
undocumented "feature".

Brendan.

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