Shouldn't you also check the status register for
completion after _every_ write to the data register?

MX

-----Original Message-----
From: l... [mailto:l...]On Behalf Of irafalovsky
Sent: Tuesday, August 08, 2006 3:04 PM
To: l...
Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
--- In l..., "Woolsey Matt"
wrote:
>
> Also, I don't see it doing a chip select, unless it's
> outside the range of code you show.
>
> MX

Yes, it is outside, I didn't want to bother audience with the code
that works... :-) Start a New Thread

We have tried that too, no difference...

--- In l..., "Woolsey Matt"
wrote:
>
> Shouldn't you also check the status register for
> completion after _every_ write to the data register?
>
> MX
>
> -----Original Message-----
> From: l... [mailto:l...]On
Behalf Of irafalovsky
> Sent: Tuesday, August 08, 2006 3:04 PM
> To: l...
> Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
> --- In l..., "Woolsey Matt"
> wrote:
> >
> > Also, I don't see it doing a chip select, unless it's
> > outside the range of code you show.
> >
> > MX
>
> Yes, it is outside, I didn't want to bother audience with the code
> that works... :-)
> Start a New Thread

We have tried sending dummy write after first read as well, with or
without clearing S1SPSR with no luck...

--- In l..., "Paul Curtis" wrote:
>
> How about waiting for some data to come back for a start?
>
> --
> Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> CrossWorks for ARM, MSP430, AVR, MAXQ, and now Cortex-M3 processors
> Start a New Thread

Should you reset the MM3 prior to selecting the chip? Seems like doing the reset
while it is selected will take it out of the SPI transfer mode.

-----Original Message-----
From: l... [mailto:l...]On Behalf Of irafalovsky
Sent: Tuesday, August 08, 2006 3:04 PM
To: l...
Subject: [lpc2000] Re: Problem with SPI1 on LPC2119

--- In lpc2000@yahoogroups .com, "Woolsey Matt"
wrote:
>
> Also, I don't see it doing a chip select, unless it's
> outside the range of code you show.
>
> MX

Yes, it is outside, I didn't want to bother audience with the code
that works... :-) Start a New Thread

I think we made the code in exact accordance to their SPI timing
sequence (Page 7 of MM3 datasheet), at least what we see on the
oscilloscope resembles what they say...

Our problem seems to be with reading 16 bits of data on MOSI, or
more precisely, with our way of working with S1SPDR...

--- In l..., "Woolsey Matt"
wrote:
>
> Should you reset the MM3 prior to selecting the chip? Seems like
doing the reset
> while it is selected will take it out of the SPI transfer mode.
>
>
> -----Original Message-----
> From: l... [mailto:l...]On
Behalf Of irafalovsky
> Sent: Tuesday, August 08, 2006 3:04 PM
> To: l...
> Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
>
> --- In lpc2000@yahoogroups 40yahoogroups.com> .com, "Woolsey Matt"
> wrote:
> >
> > Also, I don't see it doing a chip select, unless it's
> > outside the range of code you show.
> >
> > MX
>
> Yes, it is outside, I didn't want to bother audience with the code
> that works... :-)
>
>
>
>
> Start a New Thread

Tried that too, with pretty much the same outcome.

I believe we are doing everything right in terms of commanding the
peripheral to make the measurement, however we are making some sort
of mistake in the way we are attempting to read two bytes from
S1SPDR, but I have no idea what that mistake is...

--- In l..., "Woolsey Matt"
wrote:
>
> Shouldn't you also check the status register for
> completion after _every_ write to the data register?
>
> MX
>
> -----Original Message-----
> From: l... [mailto:l...]On
Behalf Of irafalovsky
> Sent: Tuesday, August 08, 2006 3:04 PM
> To: l...
> Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
> --- In l..., "Woolsey Matt"
> wrote:
> >
> > Also, I don't see it doing a chip select, unless it's
> > outside the range of code you show.
> >
> > MX
>
> Yes, it is outside, I didn't want to bother audience with the code
> that works... :-)
> Start a New Thread

Make it MISO, not MOSI...

--- In l..., "irafalovsky" wrote:
>
> I think we made the code in exact accordance to their SPI timing
> sequence (Page 7 of MM3 datasheet), at least what we see on the
> oscilloscope resembles what they say...
>
> Our problem seems to be with reading 16 bits of data on MOSI, or
> more precisely, with our way of working with S1SPDR...
>
> --- In l..., "Woolsey Matt"
> wrote:
> >
> > Should you reset the MM3 prior to selecting the chip? Seems
like
> doing the reset
> > while it is selected will take it out of the SPI transfer mode.
> >
> >
> > -----Original Message-----
> > From: l... [mailto:l...]On
> Behalf Of irafalovsky
> > Sent: Tuesday, August 08, 2006 3:04 PM
> > To: l...
> > Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
> >
> >
> >
> > --- In lpc2000@yahoogroups > 40yahoogroups.com> .com, "Woolsey Matt"
> > wrote:
> > >
> > > Also, I don't see it doing a chip select, unless it's
> > > outside the range of code you show.
> > >
> > > MX
> >
> > Yes, it is outside, I didn't want to bother audience with the
code
> > that works... :-)
> >
> >
> >
> >
> >
> >
> >
> >
> Start a New Thread

To clear the SPIF bit in S1SPSR you have to access the S1SPSR then
access the S1SPDR (ie read or write to it). You also have to shift
out a byte to receive one, and wait for the SPI status to indicate
SPIF before the received byte can be read.

I use interrupts, so I can't speak to how well polling the SPI status
register works. This code is also ignoring any errors that the SPI
may be setting as well.

Try something along these lines:

S1SPDR = 0x41; // Send Measure X command
while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
temp = S1SPDR; // Clears SPIF in S1SPSR.

while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready

S1SPDR = 0;.
while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
MM3_HB = S1SPDR; // Clears SPIF in S1SPSR.

S1SPDR = 0;
while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
MM3_LB = S1SPDR; // Clears SPIF in S1SPSR.

wMM3_X = MM3_HB;
wMM3_X = (wMM3_X << 8) | MM3_LB;

--- In l..., "irafalovsky" wrote:
>
> If we attempt to send 2 bytes after peripheral indicates available
> data, we simply get zeroes in return...
>
> Here's what code looks like:
>
> IOSET0 |= 1 << 23; // Set RESET HIGH, this is to reset the MM3
> delay(10);
> IOCLR0 |= 1 << 23; // Set RESET LOW, pulse formed
> delay(10);
> S1SPDR = 0x41; // Send Measure X command
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready
> S1SPDR = 0;
> S1SPDR = 0;
> MM3_HB = S1SPDR;
> MM3_LB = S1SPDR;
> wMM3_X = MM3_HB;
> wMM3_X = (wMM3_X << 8) | MM3_LB;
> >
> > Do you send 2 bytes out from LPC2119 to allow the SPI clock to go so
> > you can get back the 2 bytes that you are expecting?
> >
> > We have an application with LPC2138 running in slave mode and
> > receiving packets of 9 bits characters from an host processor and
> > responding with packets of 9 bits characters.
> > Naturally, in order to be able to send back the answer the LPC must
> > receive the spi clock from the master so the host processor must pump
> > out dummy characters to allow the answer to come back.
> >
> > Regards,
> >
> > Carlo Barbaro
> Start a New Thread

Thank you for your help! Unfortunately, this approach does not work
either...

Now, the question is -- is it at all possible to make LPC2119 read
16 bits sent by SPI peripheral in succession?

--- In l..., "Alan Strickland"
wrote:
>
> To clear the SPIF bit in S1SPSR you have to access the S1SPSR then
> access the S1SPDR (ie read or write to it). You also have to shift
> out a byte to receive one, and wait for the SPI status to indicate
> SPIF before the received byte can be read.
>
> I use interrupts, so I can't speak to how well polling the SPI
status
> register works. This code is also ignoring any errors that the SPI
> may be setting as well.
>
> Try something along these lines:
>
> S1SPDR = 0x41; // Send Measure X command
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> temp = S1SPDR; // Clears SPIF in S1SPSR.
>
> while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready
>
> S1SPDR = 0;.
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> MM3_HB = S1SPDR; // Clears SPIF in S1SPSR.
>
> S1SPDR = 0;
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> MM3_LB = S1SPDR; // Clears SPIF in S1SPSR.
>
> wMM3_X = MM3_HB;
> wMM3_X = (wMM3_X << 8) | MM3_LB;
>
> --- In l..., "irafalovsky" wrote:
> >
> > If we attempt to send 2 bytes after peripheral indicates
available
> > data, we simply get zeroes in return...
> >
> > Here's what code looks like:
> >
> > IOSET0 |= 1 << 23; // Set RESET HIGH, this is to reset the MM3
> > delay(10);
> > IOCLR0 |= 1 << 23; // Set RESET LOW, pulse formed
> > delay(10);
> > S1SPDR = 0x41; // Send Measure X command
> > while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> > while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready
> > S1SPDR = 0;
> > S1SPDR = 0;
> > MM3_HB = S1SPDR;
> > MM3_LB = S1SPDR;
> > wMM3_X = MM3_HB;
> > wMM3_X = (wMM3_X << 8) | MM3_LB;
> >
> >
> > >
> > > Do you send 2 bytes out from LPC2119 to allow the SPI clock to
go so
> > > you can get back the 2 bytes that you are expecting?
> > >
> > > We have an application with LPC2138 running in slave mode and
> > > receiving packets of 9 bits characters from an host processor
and
> > > responding with packets of 9 bits characters.
> > > Naturally, in order to be able to send back the answer the LPC
must
> > > receive the spi clock from the master so the host processor
must pump
> > > out dummy characters to allow the answer to come back.
> > >
> > > Regards,
> > >
> > > Carlo Barbaro
> > >
> Start a New Thread

I was never able to get the SPI engine to send 16 bits. I ended up writing my own code to do it by GPIO.
I don't believe the LPC SPI engines can do anything but 8 bit data word size.

Chris.
----- Original Message -----
From: irafalovsky
To: l...
Sent: Tuesday, August 08, 2006 9:00 PM
Subject: [lpc2000] Re: Problem with SPI1 on LPC2119
Thank you for your help! Unfortunately, this approach does not work
either...

Now, the question is -- is it at all possible to make LPC2119 read
16 bits sent by SPI peripheral in succession?

--- In l..., "Alan Strickland"
wrote:
>
> To clear the SPIF bit in S1SPSR you have to access the S1SPSR then
> access the S1SPDR (ie read or write to it). You also have to shift
> out a byte to receive one, and wait for the SPI status to indicate
> SPIF before the received byte can be read.
>
> I use interrupts, so I can't speak to how well polling the SPI
status
> register works. This code is also ignoring any errors that the SPI
> may be setting as well.
>
> Try something along these lines:
>
> S1SPDR = 0x41; // Send Measure X command
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> temp = S1SPDR; // Clears SPIF in S1SPSR.
>
> while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready
>
> S1SPDR = 0;.
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> MM3_HB = S1SPDR; // Clears SPIF in S1SPSR.
>
> S1SPDR = 0;
> while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> MM3_LB = S1SPDR; // Clears SPIF in S1SPSR.
>
> wMM3_X = MM3_HB;
> wMM3_X = (wMM3_X << 8) | MM3_LB;
>
> --- In l..., "irafalovsky" wrote:
> >
> > If we attempt to send 2 bytes after peripheral indicates
available
> > data, we simply get zeroes in return...
> >
> > Here's what code looks like:
> >
> > IOSET0 |= 1 << 23; // Set RESET HIGH, this is to reset the MM3
> > delay(10);
> > IOCLR0 |= 1 << 23; // Set RESET LOW, pulse formed
> > delay(10);
> > S1SPDR = 0x41; // Send Measure X command
> > while((S1SPSR & 0x80)!= 0x80){;;} // Wait for SPI status
> > while(!(IOPIN0 && (1 << 22))){;;} // Wait for Data Ready
> > S1SPDR = 0;
> > S1SPDR = 0;
> > MM3_HB = S1SPDR;
> > MM3_LB = S1SPDR;
> > wMM3_X = MM3_HB;
> > wMM3_X = (wMM3_X << 8) | MM3_LB;
> >
> >
> > >
> > > Do you send 2 bytes out from LPC2119 to allow the SPI clock to
go so
> > > you can get back the 2 bytes that you are expecting?
> > >
> > > We have an application with LPC2138 running in slave mode and
> > > receiving packets of 9 bits characters from an host processor
and
> > > responding with packets of 9 bits characters.
> > > Naturally, in order to be able to send back the answer the LPC
must
> > > receive the spi clock from the master so the host processor
must pump
> > > out dummy characters to allow the answer to come back.
> > >
> > > Regards,
> > >
> > > Carlo Barbaro
> > >
> >
> Start a New Thread