Hello Brendan,

Your Quote is one piece of the NXP-story but in the usermanual
(UM10139_1.pdf) the pages 265 and 272 show the following:

<<< 17.5.3 Accuracy vs. digital receiver
The AIN function must be selected in corresponding Pin
Select register (see "Pin Connect Block" on page 75)
in order to get accurate voltage readings on the monitored pin.
For pin hosting an ADC input, it is not possible to have a have
a digital function selected and yet get valid ADC readings. An
inside circuit disconnects ADC hardware from the associated
pin whenever a digital function is selected on that pin.
>>>>End Quote page 272

<<< Note: if the ADC is used, signal levels on analog input
pins must not be above the level of V3A at any time.
Otherwise, A/D converter readings will be invalid. If the
A/D converter is not used in an application then the pins
associated with A/D inputs can be used as 5 V tolerant
digital IO pins.

Warning: while the ADC pins are specified as 5 V tolerant
(see Table 58 Pin description on page 69), the analog
multiplexing in the ADC block is not. More than 3.3 V
(VDDA) +10 % should not be applied to any pin that is
selected as an ADC input, or the ADC reading will be incorrect.
If for example AD0.0 and AD0.1 are used as the ADC0 inputs and
voltage on AD0.0 = 4.5 V while AD0.1 = 2.5 V, an excessive
voltage on the AD0.0 can cause an incorrect reading of the
AD0.1, although the AD0.1 input voltage is within the right
range.
>>>>End Quote page 265
Maybe I can't see the wood because of all the trees, but for the moment
it is as clear as mud.
The main question is 'When is an input regarded as an ADC input?'.
-a- If the pin has the AD-input as an alternate function.
or
-b- Only if the pin is programmed as an AD-input.

The fact that it 'disconnects' the ADC hardware from the
associated pin gives me the impression that it should be Ok.
What I need to know is that it really works that way because
the LPC2129 had a problem in this area.

If I know more then I will share the information.

Greetings from the Netherlands,
Aalt
rfc822 Compliance issue From: added by system POTENTIAL SPAM wrote:
> I think you're taking the sensible approach (of getting it confirmed
> from NXP). There's enough ambiguity in the following statement in the
> User Manual to at least raise the question:
>
>
> Note: if the ADC is used, signal levels on analog input pins must not
> be above the level of V3A at any time. Otherwise, A/D converter
> readings will be invalid.
> Having been bitten by this particular issue (before it was documented
> anywhere) on the LPC2134, I'd get it confirmed before proceeding.
>
> Brendan.
> --- In l..., "Aalt Lokhorst" wrote:
>
>>Thiago wrote
>>
>>>I took a look on
>>> http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/
> errata.lpc2148.pdf
>
>>>There4s no recommendation for not to use these pins as 5V
>
> tolerant, even if
>
>>>they have ADC funcionallity.
>>>
>>>:)
>>>
>>>Good Lucky and I recommend you test it first.
>>>
>>>;)
>>
>>I also have the impression that it should be Ok. But I will sleep
>
> better
>
>>if it is confirmed. I have called the product specialist of our
>>distributor and he will investigate it.
>>
>>Next week I might have a better answer,
>>
>>Have a nice weekend,
>>Aalt
>>
>>--
>>=============================>>Aalt Lokhorst
>>Schut Geometrische Meettechniek bv
>>Duinkerkenstraat 21
>>9723 BN Groningen
>>P.O. Box 5225
>>9700 GE Groningen
>>The Netherlands
>>Tel: +31-50-5877877
>>Fax: +31-50-5877899
>>E-mail: Lokhorst@...
>>=============================>>
> Start a New Thread

Thanks,

Your solution is possible but requires some extra components. I think it
is a 'take it or leave' it situation.

The only advantage of using the SDA line to force the bootloader is the
the fact that it is an Open Drain. A hard pull-down will not result in
large currents.

Thanks for your information,
Aalt

rfc822 Compliance issue From: added by system POTENTIAL SPAM wrote:
> RE: Bootloader questions
>
> The simple fact is that the bootloader always runs after an external
> (hardware) reset. It is the bootloader that starts ISP mode if 0.14 is low.
> Internal hardware maps the bootloader interrupt vectors into address 0.
> If there is a hardware reset, and P0.14 is low for upto 3ms or there is no
> valid code checksum in user flash then the bootloader will run ISP mode.
> P0.14 must remain high for at least 3ms after a hardware reset to prevent a
> forced boot loader isp mode entry.
> The bootloader is not mapped into address 0 if an internal watchdog reset
> occurs or the program counter is reset to zero by software.
>
> I suggest adding a FET that disconnects your SDA signal if reset is active
> low and keeps it that way for at least 3ms after. SDA has to be pulled up
> anyway, so just put the pullup on the CPU side of the FET.
>
> You can achieve this using your reset circuit or, using just discrete
> transistors and capacitors.
>
> If you wish to use the ISP then add another FET to pull p0.14 low as and
> when required.
>
> j.
>
> -----Original Message-----
> From: l... [mailto:l...]On Behalf Of
> Aalt Lokhorst
> Sent: 07 December 2006 13:49
> To: l...
> Subject: [lpc2000] LPC2148 ADC input and bootloader questions
> Dear Readers,
>
> I like to use the LPC2148 for a project but have some questions.
>
> --Question 1--
> In the datasheets there is a note for ADC-input regarding voltages above
> VDD (just in case the pins are used as 5V tolerant input)
> For instance if P0.5/ADC0.7 and P0.4/ADC0.6 are used as ADC input then a
> voltage greater than 3.3V on ADC0.7 will disturb a measurement of ADC0.6.
>
> Now the question: If P0.5/ADC0.7 is not setup as ADC input, can it be
> used as a 5V tolerant input without disturbing the P0.4/ADC0.6 input?
>
> The User Manual writes:
> 'An inside circuit disconnects ADC hardware from the associated
> pin whenever a digital function is selected on that pin.'
>
> So I think it is Ok but I would like to hear a confirmation before
> designing the pcb.
>
> --Question 2--
> A low on P0.14 while the LPC2148 resets will force the bootloader to
> become active. P0.14 also supports the SDA function of the I2C1
> controller. Now suppose that there is a I2C communication in process,
> SDA is pulled 'low' by a I2C-device on the I2C bus and suddenly a reset
> occurs. (caused by a dip in the powersupply or something)
> Does this result in a system stop because it starts the bootloader
> instead of restarting the application?
>
> Thanks in advance,
> Aalt
>
> --
> =============================> Aalt Lokhorst
> Schut Geometrische Meettechniek bv
> Duinkerkenstraat 21
> 9723 BN Groningen
> P.O. Box 5225
> 9700 GE Groningen
> The Netherlands
> Tel: +31-50-5877877
> Fax: +31-50-5877899
> E-mail: L...@Schut.com
> =============================>
>
>
>
> Yahoo! Groups Links

--
=============================Aalt Lokhorst
Schut Geometrische Meettechniek bv
Duinkerkenstraat 21
9723 BN Groningen
P.O. Box 5225
9700 GE Groningen
The Netherlands
Tel: +31-50-5877877
Fax: +31-50-5877899
E-mail: L...@Schut.com
============================= Start a New Thread

--- In l..., "Aalt Lokhorst" wrote:
>
> Thanks,
>
> Your solution is possible but requires some extra components. I
think it
> is a 'take it or leave' it situation.
>
> The only advantage of using the SDA line to force the bootloader is the
> the fact that it is an Open Drain. A hard pull-down will not result in
> large currents.
>
> Thanks for your information,
> Aalt

There is yet another IMO simpler solution which is to replace the boot
loader itself. I have done it for others and it solves a host of
other problems too including flash programming lockouts.

Jaya Start a New Thread