Rx FIFO TRIGGER LEVEL(LPC2294)

Started by kooroshhajiani March 21, 2007
I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive
interrupt.
For example if I set it for 4 bytes(bits 7:6 in the FIFO CONTROL
REGISTER)and lets say that
In my ISR, I move 4 bytes at a time(4 access to RBTR register) to a
RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2 BYTES OF
EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND
FURTHERMORE I NEVER RECEIVED THE VERY 1st BYTE IN THE STREAM AND IF i
TRY TO MOVE LESS THAN 4 BYTES ,EVERY 4th BYTE IS MISSING AND YET IF I
MOVE 5 BYTES THE LAST 3 BYTES ARE THE SAME.
Keep in mind that I've absolutely no issue in receiving the same
stream of characters with the normal 1 byte trigger level however my
goal is to have fewer interrupts.
In LPC2294 manual, there's something about tunning and user defined
values that I don't quite understand.
Please let me know if I'm missing something?

Regards,
Koor

An Engineer's Guide to the LPC2100 Series

> -----Original Message-----
> From: l...
> [mailto:l...]On Behalf
> Of kooroshhajiani
> Sent: Wednesday, March 21, 2007 11:42 AM
> To: l...
> Subject: [lpc2000] Rx FIFO TRIGGER LEVEL(LPC2294)
> I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive
> interrupt.
> For example if I set it for 4 bytes(bits 7:6 in the FIFO CONTROL
> REGISTER)and lets say that
> In my ISR, I move 4 bytes at a time(4 access to RBTR register) to a
> RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2 BYTES OF
> EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND
> FURTHERMORE I NEVER RECEIVED THE VERY 1st BYTE IN THE STREAM AND IF i
> TRY TO MOVE LESS THAN 4 BYTES ,EVERY 4th BYTE IS MISSING AND YET IF I
> MOVE 5 BYTES THE LAST 3 BYTES ARE THE SAME.
> Keep in mind that I've absolutely no issue in receiving the same
> stream of characters with the normal 1 byte trigger level however my
> goal is to have fewer interrupts.
> In LPC2294 manual, there's something about tunning and user defined
> values that I don't quite understand.
> Please let me know if I'm missing something?
>
> Regards,
> Koor

You should read the RDR flag in the LSR register to determine when
the FIFO is empty, rather than a fixed number.

Mike
--- In l..., "Michael Anton" wrote:
>
> > -----Original Message-----
> > From: l...
> > [mailto:l...]On Behalf
> > Of kooroshhajiani
> > Sent: Wednesday, March 21, 2007 11:42 AM
> > To: l...
> > Subject: [lpc2000] Rx FIFO TRIGGER LEVEL(LPC2294)
> >
> >
> > I'm having some issue with the FIFO TRIGGER LEVEL of the UART
Receive
> > interrupt.
> > For example if I set it for 4 bytes(bits 7:6 in the FIFO
CONTROL
> > REGISTER)and lets say that
> > In my ISR, I move 4 bytes at a time(4 access to RBTR register)
to a
> > RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2
BYTES OF
> > EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND
> > FURTHERMORE I NEVER RECEIVED THE VERY 1st BYTE IN THE STREAM AND
IF i
> > TRY TO MOVE LESS THAN 4 BYTES ,EVERY 4th BYTE IS MISSING AND YET
IF I
> > MOVE 5 BYTES THE LAST 3 BYTES ARE THE SAME.
> > Keep in mind that I've absolutely no issue in receiving the same
> > stream of characters with the normal 1 byte trigger level
however my
> > goal is to have fewer interrupts.
> > In LPC2294 manual, there's something about tunning and user
defined
> > values that I don't quite understand.
> > Please let me know if I'm missing something?
> >
> > Regards,
> > Koor
> >
> > You should read the RDR flag in the LSR register to determine when
> the FIFO is empty, rather than a fixed number.
>
> Mike
>
Hi Mike
That's what I ended up doing and it works,however I wonder why? if
there's an interrupt generated every say 8 bytes and I remove them
then and there in the ISR, I should be ready for the next batch.
on a system running at 60MHZ clk it should not be an issue,
especialy when this is the only interrupt.I noticed when I am not
checking the RBR bit, whenever I come out of the interrupt the bit
called ENABLE FIFO in FIFO CONTROL register is disabled and have no
clue why it is so.That could explain the erratic behaviour mentioned
above.

Regards,
Koor
> -----Original Message-----
> From: l...
> [mailto:l...]On Behalf
> Of kooroshhajiani
> Sent: Wednesday, March 21, 2007 3:05 PM
> To: l...
> Subject: [lpc2000] Re: Rx FIFO TRIGGER LEVEL(LPC2294)
> --- In l..., "Michael Anton" wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: l...
> > > [mailto:l...]On Behalf
> > > Of kooroshhajiani
> > > Sent: Wednesday, March 21, 2007 11:42 AM
> > > To: l...
> > > Subject: [lpc2000] Rx FIFO TRIGGER LEVEL(LPC2294)
> > >
> > >
> > > I'm having some issue with the FIFO TRIGGER LEVEL of the UART
> Receive
> > > interrupt.
> > > For example if I set it for 4 bytes(bits 7:6 in the FIFO
> CONTROL
> > > REGISTER)and lets say that
> > > In my ISR, I move 4 bytes at a time(4 access to RBTR register)
> to a
> > > RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2
> BYTES OF
> > > EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND
> > > FURTHERMORE I NEVER RECEIVED THE VERY 1st BYTE IN THE STREAM AND
> IF i
> > > TRY TO MOVE LESS THAN 4 BYTES ,EVERY 4th BYTE IS MISSING AND YET
> IF I
> > > MOVE 5 BYTES THE LAST 3 BYTES ARE THE SAME.
> > > Keep in mind that I've absolutely no issue in receiving the same
> > > stream of characters with the normal 1 byte trigger level
> however my
> > > goal is to have fewer interrupts.
> > > In LPC2294 manual, there's something about tunning and user
> defined
> > > values that I don't quite understand.
> > > Please let me know if I'm missing something?
> > >
> > > Regards,
> > > Koor
> > >
> > >
> >
> > You should read the RDR flag in the LSR register to determine when
> > the FIFO is empty, rather than a fixed number.
> >
> > Mike
> >
> Hi Mike
> That's what I ended up doing and it works,however I wonder why? if
> there's an interrupt generated every say 8 bytes and I remove them
> then and there in the ISR, I should be ready for the next batch.
> on a system running at 60MHZ clk it should not be an issue,
> especialy when this is the only interrupt.I noticed when I am not
> checking the RBR bit, whenever I come out of the interrupt the bit
> called ENABLE FIFO in FIFO CONTROL register is disabled and have no
> clue why it is so.That could explain the erratic behaviour mentioned
> above.
>
> Regards,
> Koor
>

There is also the case of receiving an Rx timeout interrupt, in
which case the FIFO will contain less characters than the trigger
threshold. This could be what is causing your problem, which is
why reading the RDR flag works.

The manual does indicate that if it is an RDA interrupt, you can
read the number of bytes that the FIFO trigger level is set to.
But, you will need to handle the CTI interrupt differently, by
reading the RDR flag, since you don't know how many bytes are in
the FIFO. My ISR handler does the same thing for both CTI, and
RDA, which is to keep reading data until the RDR flag is cleared.

Generally, you would set the FIFO to the largest value, to minimize
interrupt overhead. The CTI interrupt handles reception for packets
that are not an integer multiple of your FIFO size.

Mike