can someone help me, I am confused by the datasheet and by what I
appear to be getting when setting up the clocks.
I am using FreeRTOS.
Basically I have some simple code that just flashes an LED and I am
now trying to get UART0 up and running but the baudrate is wrong.
I think this is because CCLK is not what I think it is.
My main XTAL is 4Mhz and I will need to use the USB so luckily the
lpc2368 user manual gives an example of setting up the PLL with this
crystal. (example 1 page 45)
>From the datasheet. FCCO = (2 x M x FIn)/N
So I have M = 36, N = 1 giving FCCO of 288Mhz.
The data sheet then goes on to say use 6 for USBCLKCFG giving 48Mhz
and 5 for CCLKCFG giving 57.6Mhz.
from the datasheet
> The potential CPU clock rate can be determined by
dividing FCCO
> by the desired CPU frequency: 288 106 / 60 106 = 4.8.
> The nearest integer value for the CPU Clock Divider is then 5,
> giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
Now, the first bit that is not clear. The data sheet says CCLKCFG
register must be odd or incorrect operation may occur, so ok 5 is alright.
It then says CCLK is the PLL output divided by CCLKSEL+1, but if
CCLKSEL is 5, then the CPU clock will be 48 Mhz and not 57.6Mhz.
So which part is correct. I guess as my baudrate is wrong, I do
probably have a CCLK speed of only 48Mhz.
I am missing something here ? The datasheet appears to be wrong.
thanks for any help
Ben
configure LPC2368 CPU clock and UART clock
Started by ●October 4, 2007
Reply by ●October 4, 20072007-10-04
--- In l..., "rtstofer" wrote:
>
> --- In l..., "ben_fnr" wrote:
> >
> > can someone help me, I am confused by the datasheet and by what I
> > appear to be getting when setting up the clocks.
> >
> > I am using FreeRTOS.
> > Basically I have some simple code that just flashes an LED and I am
> > now trying to get UART0 up and running but the baudrate is wrong.
> >
> > I think this is because CCLK is not what I think it is.
> >
> > My main XTAL is 4Mhz and I will need to use the USB so luckily the
> > lpc2368 user manual gives an example of setting up the PLL with this
> > crystal. (example 1 page 45)
> >
> > From the datasheet. FCCO = (2 x M x FIn)/N
> >
> > So I have M = 36, N = 1 giving FCCO of 288Mhz.
> >
> > The data sheet then goes on to say use 6 for USBCLKCFG giving 48Mhz
> > and 5 for CCLKCFG giving 57.6Mhz.
> >
> > from the datasheet
> >
> > > The potential CPU clock rate can be determined by dividing FCCO
> > > by the desired CPU frequency: 288 106 / 60 106 = 4.8.
> > > The nearest integer value for the CPU Clock Divider is then 5,
> > > giving us 57.6 MHz as the nearest value to the desired CPU clock
rate.
> >
> > Now, the first bit that is not clear. The data sheet says CCLKCFG
> > register must be odd or incorrect operation may occur, so ok 5 is
> alright.
> >
> > It then says CCLK is the PLL output divided by CCLKSEL+1, but if
> > CCLKSEL is 5, then the CPU clock will be 48 Mhz and not 57.6Mhz.
> >
> > So which part is correct. I guess as my baudrate is wrong, I do
> > probably have a CCLK speed of only 48Mhz.
> >
> > I am missing something here ? The datasheet appears to be wrong.
> >
> > thanks for any help
> > Ben
> >
>
>
> I am looking at the LPC2468 user manual and I think you have it wrong
> and the user manual is correct.
>
> Looking at the last paragraph of Example 1 - page 41:
>
> In order to get 60 MHz AND 48 MHz (REQUIRED for USB), the only
> possible FCCO rate is 480 MHz (240 MHz is too low for the CCO).
> Divide by 10 to get 48 MHz and by 8 for 60 Mhz.
>
> N = 1, M = 60
>
> But, we don't stuff M and N in PLLCFG, we stuff N-1 and M-1 (page 40 -
> 5.12.4)
>
> When you set CCLKSEL, set it to 7 and when the PLL output (480 MHz) is
> divided by (7 + 1 or 8) you will get 60 MHz.
>
> Similar for USBCLKCFG with we want to divide by 10 so we enter a value
> of 9.
>
> Whether you choose 60 MHz or 57.6 MHz may not be important. Just make
> sure you have the fractional baud rate generator set correctly.
>
> I have an LPC2148 with a 12 MHz crystal so I choose N=1, M=5 to get 60
> MHz. I set the pclk to 1/4 cclk so the peripherals run at 15 MHz. So,
> I set the main divider (U0DLL) to 5 (U0DLM = 0), MULVAL 8 and
> DIVADDVAL to 13 to get pretty close to 115200 baud. It works...
>
>
> Richard
>
Strictly speaking I did what the manual said, but yes it is wrong. The
register description is correct and the example given is wrong. Anyway
I am now putting 3 into CCLKCFG (divide by 4) to give 72Mhz CCLK.
Recalculating the baudrate divisors now work ok based on 72Mhz CCLK.
This is my first foray into the LPC family, up until now I have been
using ST's Arm7 family.
I have yet to find a datasheet/user manual for a micro that is
accurate. They all seem to either have conflicting information or are
so ambiguous that a fair amount of trail and error is needed and then
you can't be sure things are working for the right reasons.
Ben
>
> --- In l..., "ben_fnr" wrote:
> >
> > can someone help me, I am confused by the datasheet and by what I
> > appear to be getting when setting up the clocks.
> >
> > I am using FreeRTOS.
> > Basically I have some simple code that just flashes an LED and I am
> > now trying to get UART0 up and running but the baudrate is wrong.
> >
> > I think this is because CCLK is not what I think it is.
> >
> > My main XTAL is 4Mhz and I will need to use the USB so luckily the
> > lpc2368 user manual gives an example of setting up the PLL with this
> > crystal. (example 1 page 45)
> >
> > From the datasheet. FCCO = (2 x M x FIn)/N
> >
> > So I have M = 36, N = 1 giving FCCO of 288Mhz.
> >
> > The data sheet then goes on to say use 6 for USBCLKCFG giving 48Mhz
> > and 5 for CCLKCFG giving 57.6Mhz.
> >
> > from the datasheet
> >
> > > The potential CPU clock rate can be determined by dividing FCCO
> > > by the desired CPU frequency: 288 106 / 60 106 = 4.8.
> > > The nearest integer value for the CPU Clock Divider is then 5,
> > > giving us 57.6 MHz as the nearest value to the desired CPU clock
rate.
> >
> > Now, the first bit that is not clear. The data sheet says CCLKCFG
> > register must be odd or incorrect operation may occur, so ok 5 is
> alright.
> >
> > It then says CCLK is the PLL output divided by CCLKSEL+1, but if
> > CCLKSEL is 5, then the CPU clock will be 48 Mhz and not 57.6Mhz.
> >
> > So which part is correct. I guess as my baudrate is wrong, I do
> > probably have a CCLK speed of only 48Mhz.
> >
> > I am missing something here ? The datasheet appears to be wrong.
> >
> > thanks for any help
> > Ben
> >
>
>
> I am looking at the LPC2468 user manual and I think you have it wrong
> and the user manual is correct.
>
> Looking at the last paragraph of Example 1 - page 41:
>
> In order to get 60 MHz AND 48 MHz (REQUIRED for USB), the only
> possible FCCO rate is 480 MHz (240 MHz is too low for the CCO).
> Divide by 10 to get 48 MHz and by 8 for 60 Mhz.
>
> N = 1, M = 60
>
> But, we don't stuff M and N in PLLCFG, we stuff N-1 and M-1 (page 40 -
> 5.12.4)
>
> When you set CCLKSEL, set it to 7 and when the PLL output (480 MHz) is
> divided by (7 + 1 or 8) you will get 60 MHz.
>
> Similar for USBCLKCFG with we want to divide by 10 so we enter a value
> of 9.
>
> Whether you choose 60 MHz or 57.6 MHz may not be important. Just make
> sure you have the fractional baud rate generator set correctly.
>
> I have an LPC2148 with a 12 MHz crystal so I choose N=1, M=5 to get 60
> MHz. I set the pclk to 1/4 cclk so the peripherals run at 15 MHz. So,
> I set the main divider (U0DLL) to 5 (U0DLM = 0), MULVAL 8 and
> DIVADDVAL to 13 to get pretty close to 115200 baud. It works...
>
>
> Richard
>
Strictly speaking I did what the manual said, but yes it is wrong. The
register description is correct and the example given is wrong. Anyway
I am now putting 3 into CCLKCFG (divide by 4) to give 72Mhz CCLK.
Recalculating the baudrate divisors now work ok based on 72Mhz CCLK.
This is my first foray into the LPC family, up until now I have been
using ST's Arm7 family.
I have yet to find a datasheet/user manual for a micro that is
accurate. They all seem to either have conflicting information or are
so ambiguous that a fair amount of trail and error is needed and then
you can't be sure things are working for the right reasons.
Ben
Reply by ●October 5, 20072007-10-05
On Thu, 4 Oct 2007, ben_fnr wrote:
> This is my first foray into the LPC family, up until now I have been
> using ST's Arm7 family.
> I have yet to find a datasheet/user manual for a micro that is accurate.
Yeah, it bites and is as inevitable as Murphy's Law.
At least make sure you have the Rev *2* of the LPC21XX, as well as the errata.
-Kenny
--
Kenneth R. Crudup Sr. SW Engineer, Scott County Consulting, Los Angeles
O: 3630 S. Sepulveda Blvd. #138, L.A., CA 90034-6809 (888) 454-8181
> This is my first foray into the LPC family, up until now I have been
> using ST's Arm7 family.
> I have yet to find a datasheet/user manual for a micro that is accurate.
Yeah, it bites and is as inevitable as Murphy's Law.
At least make sure you have the Rev *2* of the LPC21XX, as well as the errata.
-Kenny
--
Kenneth R. Crudup Sr. SW Engineer, Scott County Consulting, Los Angeles
O: 3630 S. Sepulveda Blvd. #138, L.A., CA 90034-6809 (888) 454-8181
Reply by ●October 5, 20072007-10-05
--- In l..., "ben_fnr" wrote:
>
> can someone help me, I am confused by the datasheet and by what I
> appear to be getting when setting up the clocks.
>
> I am using FreeRTOS.
> Basically I have some simple code that just flashes an LED and I am
> now trying to get UART0 up and running but the baudrate is wrong.
>
> I think this is because CCLK is not what I think it is.
>
> My main XTAL is 4Mhz and I will need to use the USB so luckily the
> lpc2368 user manual gives an example of setting up the PLL with this
> crystal. (example 1 page 45)
>
> From the datasheet. FCCO = (2 x M x FIn)/N
>
> So I have M = 36, N = 1 giving FCCO of 288Mhz.
>
> The data sheet then goes on to say use 6 for USBCLKCFG giving 48Mhz
> and 5 for CCLKCFG giving 57.6Mhz.
>
> from the datasheet
>
> > The potential CPU clock rate can be determined by dividing FCCO
> > by the desired CPU frequency: 288 106 / 60 106 = 4.8.
> > The nearest integer value for the CPU Clock Divider is then 5,
> > giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
>
> Now, the first bit that is not clear. The data sheet says CCLKCFG
> register must be odd or incorrect operation may occur, so ok 5 is
alright.
>
> It then says CCLK is the PLL output divided by CCLKSEL+1, but if
> CCLKSEL is 5, then the CPU clock will be 48 Mhz and not 57.6Mhz.
>
> So which part is correct. I guess as my baudrate is wrong, I do
> probably have a CCLK speed of only 48Mhz.
>
> I am missing something here ? The datasheet appears to be wrong.
>
> thanks for any help
> Ben
>
I am looking at the LPC2468 user manual and I think you have it wrong
and the user manual is correct.
Looking at the last paragraph of Example 1 - page 41:
In order to get 60 MHz AND 48 MHz (REQUIRED for USB), the only
possible FCCO rate is 480 MHz (240 MHz is too low for the CCO).
Divide by 10 to get 48 MHz and by 8 for 60 Mhz.
N = 1, M = 60
But, we don't stuff M and N in PLLCFG, we stuff N-1 and M-1 (page 40 -
5.12.4)
When you set CCLKSEL, set it to 7 and when the PLL output (480 MHz) is
divided by (7 + 1 or 8) you will get 60 MHz.
Similar for USBCLKCFG with we want to divide by 10 so we enter a value
of 9.
Whether you choose 60 MHz or 57.6 MHz may not be important. Just make
sure you have the fractional baud rate generator set correctly.
I have an LPC2148 with a 12 MHz crystal so I choose N=1, M=5 to get 60
MHz. I set the pclk to 1/4 cclk so the peripherals run at 15 MHz. So,
I set the main divider (U0DLL) to 5 (U0DLM = 0), MULVAL 8 and
DIVADDVAL to 13 to get pretty close to 115200 baud. It works...
Richard
>
> can someone help me, I am confused by the datasheet and by what I
> appear to be getting when setting up the clocks.
>
> I am using FreeRTOS.
> Basically I have some simple code that just flashes an LED and I am
> now trying to get UART0 up and running but the baudrate is wrong.
>
> I think this is because CCLK is not what I think it is.
>
> My main XTAL is 4Mhz and I will need to use the USB so luckily the
> lpc2368 user manual gives an example of setting up the PLL with this
> crystal. (example 1 page 45)
>
> From the datasheet. FCCO = (2 x M x FIn)/N
>
> So I have M = 36, N = 1 giving FCCO of 288Mhz.
>
> The data sheet then goes on to say use 6 for USBCLKCFG giving 48Mhz
> and 5 for CCLKCFG giving 57.6Mhz.
>
> from the datasheet
>
> > The potential CPU clock rate can be determined by dividing FCCO
> > by the desired CPU frequency: 288 106 / 60 106 = 4.8.
> > The nearest integer value for the CPU Clock Divider is then 5,
> > giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
>
> Now, the first bit that is not clear. The data sheet says CCLKCFG
> register must be odd or incorrect operation may occur, so ok 5 is
alright.
>
> It then says CCLK is the PLL output divided by CCLKSEL+1, but if
> CCLKSEL is 5, then the CPU clock will be 48 Mhz and not 57.6Mhz.
>
> So which part is correct. I guess as my baudrate is wrong, I do
> probably have a CCLK speed of only 48Mhz.
>
> I am missing something here ? The datasheet appears to be wrong.
>
> thanks for any help
> Ben
>
I am looking at the LPC2468 user manual and I think you have it wrong
and the user manual is correct.
Looking at the last paragraph of Example 1 - page 41:
In order to get 60 MHz AND 48 MHz (REQUIRED for USB), the only
possible FCCO rate is 480 MHz (240 MHz is too low for the CCO).
Divide by 10 to get 48 MHz and by 8 for 60 Mhz.
N = 1, M = 60
But, we don't stuff M and N in PLLCFG, we stuff N-1 and M-1 (page 40 -
5.12.4)
When you set CCLKSEL, set it to 7 and when the PLL output (480 MHz) is
divided by (7 + 1 or 8) you will get 60 MHz.
Similar for USBCLKCFG with we want to divide by 10 so we enter a value
of 9.
Whether you choose 60 MHz or 57.6 MHz may not be important. Just make
sure you have the fractional baud rate generator set correctly.
I have an LPC2148 with a 12 MHz crystal so I choose N=1, M=5 to get 60
MHz. I set the pclk to 1/4 cclk so the peripherals run at 15 MHz. So,
I set the main divider (U0DLL) to 5 (U0DLM = 0), MULVAL 8 and
DIVADDVAL to 13 to get pretty close to 115200 baud. It works...
Richard
Reply by ●October 5, 20072007-10-05
> This is my first foray into the LPC family, up until
now I have been
> using ST's Arm7 family.
> I have yet to find a datasheet/user manual for a micro that is
> accurate. They all seem to either have conflicting information or are
> so ambiguous that a fair amount of trail and error is needed and then
> you can't be sure things are working for the right reasons.
>
> Ben
>
The learning curve is quite steep. The more complexity a device
presents, the harder it is to write the manual. I know for certain
that I didn't have as many problems getting up to speed with the 8080.
Even if the manual is correct and well understood, the silicon may not
cooperate. That's where it really gets difficult. All the errata...
I'm the kind of guy that keeps kicking at things until they work.
Kind of like the two rules of soccer: if it moves, kick it! If it
doesn't, kick it harder!
Richard
Richard
> using ST's Arm7 family.
> I have yet to find a datasheet/user manual for a micro that is
> accurate. They all seem to either have conflicting information or are
> so ambiguous that a fair amount of trail and error is needed and then
> you can't be sure things are working for the right reasons.
>
> Ben
>
The learning curve is quite steep. The more complexity a device
presents, the harder it is to write the manual. I know for certain
that I didn't have as many problems getting up to speed with the 8080.
Even if the manual is correct and well understood, the silicon may not
cooperate. That's where it really gets difficult. All the errata...
I'm the kind of guy that keeps kicking at things until they work.
Kind of like the two rules of soccer: if it moves, kick it! If it
doesn't, kick it harder!
Richard
Richard
