--- In l..., "czesio_lpc" wrote:
>
> Hello,
>
> I am working with the system that uses the AT45DB161D serial flash
> memory for data storage. In original design of the hardware,
> the /RESET pin of the flash was connected directly to the common
> Reset net of the system. For the reset signal generation the
> ADM6713TAKSZ-REEL-7 chip is used. The signal resets at the same time
> the CPU (LPC2378) as well as the flash, on the power-on of the
> system.
>
> During development I use the JTAG probe that obviously is able to
> reset the CPU (but at the same time also the flash memory according
> to the hardware design). After such reset (without power cycle of the
> system) we observe strange behavior of the chip. The write operation
> performed page by page (in 528 byte addressing fashion) fails on 27th
> write cycle as well as on 2077th. The start page doesn't matter. When
> we disconnected the track, form the common reset net to the /RESET
> pin of the chip, the system started to work correctly.
>
> Do you see any reason why the AT45DB161D chip should behave
> differently when reset externally without power cycle?
>
> Thank you in advance from any suggestion,
>
> Greetings
> Czesio
>

Have you observed the startup time for the flash chip? I encountered a
similar issue with the configuration of a FPGA via a serial flash
(Atmel flash). A minimum of 50ms of time after the reset had to be
observed until it was allowed to use the chip. Maybe you have a
similar issue?

With kind regards, Bart



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Hi Czesio!

I have a design with the same configuration ( LPC2378 + AT45DB161 ), and
both reset- lines are connected together. No problems with it. So I
suggest to look the 20 mS startup time, before trying to issue a command
to the AT45DB161D.

Best Regards!

German
boombox666 escribi
>
> --- In l... ,
> "czesio_lpc" wrote:
> >
> > Hello,
> >
> > I am working with the system that uses the AT45DB161D serial flash
> > memory for data storage. In original design of the hardware,
> > the /RESET pin of the flash was connected directly to the common
> > Reset net of the system. For the reset signal generation the
> > ADM6713TAKSZ-REEL-7 chip is used. The signal resets at the same time
> > the CPU (LPC2378) as well as the flash, on the power-on of the
> > system.
> >
> > During development I use the JTAG probe that obviously is able to
> > reset the CPU (but at the same time also the flash memory according
> > to the hardware design). After such reset (without power cycle of the
> > system) we observe strange behavior of the chip. The write operation
> > performed page by page (in 528 byte addressing fashion) fails on 27th
> > write cycle as well as on 2077th. The start page doesn't matter. When
> > we disconnected the track, form the common reset net to the /RESET
> > pin of the chip, the system started to work correctly.
> >
> > Do you see any reason why the AT45DB161D chip should behave
> > differently when reset externally without power cycle?
> >
> > Thank you in advance from any suggestion,
> >
> > Greetings
> > Czesio
> > Have you observed the startup time for the flash chip? I encountered a
> similar issue with the configuration of a FPGA via a serial flash
> (Atmel flash). A minimum of 50ms of time after the reset had to be
> observed until it was allowed to use the chip. Maybe you have a
> similar issue?
>
> With kind regards, Bart
>
> Start a New Thread