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SPI, SSP Specification Differences

Started by tmasyl January 15, 2008
Greetings:

I find the LPC2138 User Guide rather vague for the SPI, SSP
peripherals. I wonder if there is additional support information for
these peripherals that I don't have? The following questions come to mind:

1) It appears the SSP offers higher performance than the SPI in
that the SSP clock divider can be set at minimum of 2 compared to 8
for the SPI. In the case of a 50 MHz peripheral clock rate this would
suggest the SSP can be run at 25 Mb/S. Is this possible with the LPC2138?

2) There is mention of a FIFO buffer for the SSP but not for the
SPI. I noticed some code examples that show the FIFO buffer as 8
words in size - is this correct?

3) With the Pin Connect Block set for SPI/SSP operation is it
necessary to also set the GPIO direction register for the associated
pin data direction or does the GPIO direction register only have
impact on pins set to GPIO operation?

4) Is there an NXP document that describes the SPI/SSP
peripherals in detail with block diagrams, specifications, FIFO
register addresses, etc?

Many thanks in advance for any help!

Tom Alldread

An Engineer's Guide to the LPC2100 Series