> To cut a long post short, if it's less than 255 shove it in DLL and
> set DLM to 0
>

Before I get pulled up by the other experienced developers, I meant:

'To cut a long post short, if it's less than 256 shove it in DLL and
set DLM to 0'

Oops,
Martin

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OK guys,

I have transmission. The problem was in the code, but it was also a
bad com port on my desktop. I used my laptop and it worked. I have
one last problem, it probably lies within how UART works, but I really
appreciate everything.

Thank You,
Ryan Dawson

--- In l..., "mjames_doveridge" wrote:
>
> --- In l..., "Ryan Dawson" wrote:
> >
> > Thanks for all of the quick replies. This is the first time I have
> > posted here, and I am very impressed. Wow I guess programming late
> > at night is not a good idea for me. I will fix the ASCII error and
> > the terrible for loop I made.
>
> Apart from the points made by the other posters, you really ought to
> use appropriate types. A function called 'putchar' really should take
> a parameter of type 'char'. If you are using a loop to generate a
> stream of incrementing characters, you should use a loop counter of
> type 'char'. If you had used the appropriate types, instead of just
> reaching for 'int', you would have found it impossible to set '20' as
> a loop terminator because '20' is illegal as a character literal.
> As for the core clock issue, I am not
> > sure what to do. I am unsure of what DLL does. I have read this
> > from a pdf.
> >
> > The UART0 Divisor Latch is part of the UART0 Baud Rate Generator and
> > holds the value used to divide the VPB clock (pclk) in
> > order to produce the baud rate clock, which must be 16x the desired
> > baud rate. The U0DLL and U0DLM registers together form
> > a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor
> > and U0DLM contains the higher 8 bits of the divisor. A `h0000
> > value is treated like a `h0001 value as division by zero is not
> > allowed.The Divisor Latch Access Bit (DLAB) in U0LCR must be
> > one in order to access the UART0 Divisor Latches.
> >
> > But I am unsure of what this means.
> > Which bit are you unsure of? The UART hardware must generate the tx
> character bits at the correct rate and must also sample the incoming
> rx bits at a rate that ensures that the start/data/stop bits are
> interpreted correctly - this needs a baud rate clock of 16x the baud
> rate. The baud rate clock is derived from the peripheral clock by a
> programmable divider. The peripheral clock is used to count down an
> internal divider register to zero, at which time the baud rate clock
> is toggled, the internal divider register reloaded from the divisor
> latch and the countdown restarts. The above text from the user manual
> describes this and how to set the 16-bit divisor latch value in two
> 8-bit loads when the DLAB control bit in the U0LCR is set.
>
> Rgds,
> Martin
>

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