I'm new to the chip evaluating if its SPI bus can be used for interfacing
with some components.
>From all the examples I've read on this forum, it
seems everyone is running the SSEL line in GPIO mode and not the actual SSEL
function.
I wrote up a simple example with the LPC as the Master and the MOSI, SCK and
SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL
line does not bounce with data.
The SSEL line is configured as SSEL and not GPIO.
I just need to clarify if the hardware SSEL does not bounce with data. It has to
be configured as a GPIO and controlled manually(High-Low-High)
Thanks!
LPC2378 SPI SSEL
Started by ●March 31, 2009
Reply by ●March 31, 20092009-03-31
bluehash9 wrote:
> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
>
> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
> The SSEL line is configured as SSEL and not GPIO.
>
> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
>
> Thanks!
>
The only time the SSEL will toggle is if you use the SSP and not the
SPI mode (if you have one). Otherwise you will need to toggle it manually.
regards,
Charles
> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
>
> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
> The SSEL line is configured as SSEL and not GPIO.
>
> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
>
> Thanks!
>
The only time the SSEL will toggle is if you use the SSP and not the
SPI mode (if you have one). Otherwise you will need to toggle it manually.
regards,
Charles
Reply by ●March 31, 20092009-03-31
Reply by ●March 31, 20092009-03-31
On Tue, 31 Mar 2009 10:33:34 -0400, you wrote:
>bluehash9 wrote:
>> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
>>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
>>
>> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
>> The SSEL line is configured as SSEL and not GPIO.
>>
>> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
>>
>> Thanks!
>>The only time the SSEL will toggle is if you use the SSP and not the
>SPI mode (if you have one). Otherwise you will need to toggle it manually.
Another issue, mostly noticeable when not using interrupts, is that if you keep the SSP busy wiiith
data, SSEL will be one long pulse, but if it goes idle, SSEL goes high between words. This means you
can see 'gaps' in SSEL if you don't keep up with the data rate. It also means you can't enforce gaps
between words other than by adding time delays
>bluehash9 wrote:
>> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
>>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
>>
>> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
>> The SSEL line is configured as SSEL and not GPIO.
>>
>> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
>>
>> Thanks!
>>The only time the SSEL will toggle is if you use the SSP and not the
>SPI mode (if you have one). Otherwise you will need to toggle it manually.
Another issue, mostly noticeable when not using interrupts, is that if you keep the SSP busy wiiith
data, SSEL will be one long pulse, but if it goes idle, SSEL goes high between words. This means you
can see 'gaps' in SSEL if you don't keep up with the data rate. It also means you can't enforce gaps
between words other than by adding time delays
Reply by ●March 31, 20092009-03-31
Hi Mike,
--- In l..., Mike Harrison wrote:
>
> On Tue, 31 Mar 2009 10:33:34 -0400, you wrote:
>
> >bluehash9 wrote:
> >> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
> >>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
> >>
> >> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
> >> The SSEL line is configured as SSEL and not GPIO.
> >>
> >> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
> >>
> >> Thanks!
> >>
> >
> >The only time the SSEL will toggle is if you use the SSP and not the
> >SPI mode (if you have one). Otherwise you will need to toggle it manually.
> Another issue, mostly noticeable when not using interrupts, is that if you keep the SSP busy wiiith
> data, SSEL will be one long pulse, but if it goes idle, SSEL goes high between words. This means you
> can see 'gaps' in SSEL if you don't keep up with the data rate. It also means you can't enforce gaps
> between words other than by adding time delays
>
The SPI mode parameter CPHA determines whether or not SSEL will be inactive between frames. CPHA=1: SSEL is continuosly active as long as you feed the TX FIFO. CPHA=0: SSEL goes high between frames even if you keep the TX FIFO full.
Regards,
Rolf
--- In l..., Mike Harrison wrote:
>
> On Tue, 31 Mar 2009 10:33:34 -0400, you wrote:
>
> >bluehash9 wrote:
> >> I'm new to the chip evaluating if its SPI bus can be used for interfacing with some components.
> >>>From all the examples I've read on this forum, it seems everyone is running the SSEL line in GPIO mode and not the actual SSEL function.
> >>
> >> I wrote up a simple example with the LPC as the Master and the MOSI, SCK and SSEL connected to a scope. The Clock and the MOSI both look great, but the SSEL line does not bounce with data.
> >> The SSEL line is configured as SSEL and not GPIO.
> >>
> >> I just need to clarify if the hardware SSEL does not bounce with data. It has to be configured as a GPIO and controlled manually(High-Low-High)
> >>
> >> Thanks!
> >>
> >
> >The only time the SSEL will toggle is if you use the SSP and not the
> >SPI mode (if you have one). Otherwise you will need to toggle it manually.
> Another issue, mostly noticeable when not using interrupts, is that if you keep the SSP busy wiiith
> data, SSEL will be one long pulse, but if it goes idle, SSEL goes high between words. This means you
> can see 'gaps' in SSEL if you don't keep up with the data rate. It also means you can't enforce gaps
> between words other than by adding time delays
>
The SPI mode parameter CPHA determines whether or not SSEL will be inactive between frames. CPHA=1: SSEL is continuosly active as long as you feed the TX FIFO. CPHA=0: SSEL goes high between frames even if you keep the TX FIFO full.
Regards,
Rolf
