Hi there,
Please could you explain to me why the value -0x0FF0 is choosen
for IRQ processing, in the startup.s file. I have read that for earlier version
of VIC used in LPC controllers this value was -0x0120
;LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
Regards,
Chetan
Regarding IRQ interrupt
Started by ●June 25, 2009
Reply by ●June 25, 20092009-06-25
chetan_r_prabhu schrieb:
> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> ;LDR PC, IRQ_Addr
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
Depends on where the VIC is placed. Either at 0-0x120 or 0-0xff0.
Check the respective LPC2xxx manual.
--
42Bastian
------------------
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> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> ;LDR PC, IRQ_Addr
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
Depends on where the VIC is placed. Either at 0-0x120 or 0-0xff0.
Check the respective LPC2xxx manual.
--
42Bastian
------------------
Parts of this email are written with invisible ink.
Note: SPAM-only account, direct mail to bs42@...
Reply by ●June 25, 20092009-06-25
--- In l..., "chetan_r_prabhu" wrote:
>
> Hi there,
>
> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> ;LDR PC, IRQ_Addr
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
>
> Regards,
> Chetan
>
Here are the comments I put in my startup.s file...
/* Load the PC with the interrupt vector address read from the NXP LPC2103
* VICaddr register (0xFFFFF030).
*
* NOTE: The ARM7 CPU has a 3-stage pipeline (fetch, instruction decode,
* execute). As a result, the value in the PC is two instructions ahead
* of instruction execution (8 bytes becase this is 32-bit ARM code and
* each instruction is 4 bytes).
*
* NOTE: Look at the startup.lst file to see that the address of the
* "LDR PC, [PC, #-0xFF0]" instruction below is 0x00000018
*
* NOTE: (PC + 0x8) - 0xFF0 = 0x00000018 - 0x00000FF0 = 0xFFFFF030
*/
LDR PC, [PC, #-0xFF0]
LDR PC, _fiq
>
> Hi there,
>
> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> ;LDR PC, IRQ_Addr
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
>
> Regards,
> Chetan
>
Here are the comments I put in my startup.s file...
/* Load the PC with the interrupt vector address read from the NXP LPC2103
* VICaddr register (0xFFFFF030).
*
* NOTE: The ARM7 CPU has a 3-stage pipeline (fetch, instruction decode,
* execute). As a result, the value in the PC is two instructions ahead
* of instruction execution (8 bytes becase this is 32-bit ARM code and
* each instruction is 4 bytes).
*
* NOTE: Look at the startup.lst file to see that the address of the
* "LDR PC, [PC, #-0xFF0]" instruction below is 0x00000018
*
* NOTE: (PC + 0x8) - 0xFF0 = 0x00000018 - 0x00000FF0 = 0xFFFFF030
*/
LDR PC, [PC, #-0xFF0]
LDR PC, _fiq
Reply by ●June 25, 20092009-06-25
It is a standart constant depending the LPC2xxx.
It is -0x0FF0 on LPC 21xx
and -0x0120 on LPC 23xx
for exemple.
2009/6/25 tcirobot
> --- In l... ,
> "chetan_r_prabhu" wrote:
> >
> > Hi there,
> >
> > Please could you explain to me why the value -0x0FF0 is choosen
> > for IRQ processing, in the startup.s file. I have read that for earlier
> version of VIC used in LPC controllers this value was -0x0120
> >
> > ;LDR PC, IRQ_Addr
> > LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
> >
> > Regards,
> > Chetan
> > Here are the comments I put in my startup.s file...
>
> /* Load the PC with the interrupt vector address read from the NXP LPC2103
> * VICaddr register (0xFFFFF030).
> *
> * NOTE: The ARM7 CPU has a 3-stage pipeline (fetch, instruction decode,
> * execute). As a result, the value in the PC is two instructions ahead
> * of instruction execution (8 bytes becase this is 32-bit ARM code and
> * each instruction is 4 bytes).
> *
> * NOTE: Look at the startup.lst file to see that the address of the
> * "LDR PC, [PC, #-0xFF0]" instruction below is 0x00000018
> *
> * NOTE: (PC + 0x8) - 0xFF0 = 0x00000018 - 0x00000FF0 = 0xFFFFF030
> */
> LDR PC, [PC, #-0xFF0]
> LDR PC, _fiq
>
>
>
It is -0x0FF0 on LPC 21xx
and -0x0120 on LPC 23xx
for exemple.
2009/6/25 tcirobot
> --- In l... ,
> "chetan_r_prabhu" wrote:
> >
> > Hi there,
> >
> > Please could you explain to me why the value -0x0FF0 is choosen
> > for IRQ processing, in the startup.s file. I have read that for earlier
> version of VIC used in LPC controllers this value was -0x0120
> >
> > ;LDR PC, IRQ_Addr
> > LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
> >
> > Regards,
> > Chetan
> > Here are the comments I put in my startup.s file...
>
> /* Load the PC with the interrupt vector address read from the NXP LPC2103
> * VICaddr register (0xFFFFF030).
> *
> * NOTE: The ARM7 CPU has a 3-stage pipeline (fetch, instruction decode,
> * execute). As a result, the value in the PC is two instructions ahead
> * of instruction execution (8 bytes becase this is 32-bit ARM code and
> * each instruction is 4 bytes).
> *
> * NOTE: Look at the startup.lst file to see that the address of the
> * "LDR PC, [PC, #-0xFF0]" instruction below is 0x00000018
> *
> * NOTE: (PC + 0x8) - 0xFF0 = 0x00000018 - 0x00000FF0 = 0xFFFFF030
> */
> LDR PC, [PC, #-0xFF0]
> LDR PC, _fiq
>
>
>
Reply by ●June 25, 20092009-06-25
--- In l..., "chetan_r_prabhu" wrote:
>
> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
>
(Actually it is the other way around - 0x0120 is used in the *later*, LPC2300/2400, controllers)
The reason for the two different values is because NXP changed the location of the 'Vector Address Register' when they designed the LPC23xx/LPC24xx MCUs.
If you want to know the significance of the particular values -0x0120 and -0x0FF0 then read on:
In the LDR instruction above the value #-0x0FF0 denotes an offset calculated from the current value of the program counter (PC). Note that the particular LDR instruction you have quoted is located at address 0x18 (the IRQ interrupt vector).
Hence PC, #-0x0FF0 = (PC + 8 -0x0FF0) = (0x18 + 8 - 0x0FF0) = 0xFFFFF030 which is the location of VICVectAddr, the Vector Address register!
Similarly, for the LPC23xx/24xx MCUs:
PC, #-0x0120 = (PC + 8 -0x0120) = (0x18 + 8 -0x0120) = 0xFFFFFF00 which is the location of VICAddress (which is what the Vector Address register is now called).
What this all means is that when an IRQ causes the processor to branch to address 0x18, the PC is then loaded with the value that is contained in the location VICVectAddr / VICAddress. i.e. execution then continues with the interrupt handler whose address has been stored there by the VIC system.
P.S. If you are wondering where the '+ 8' comes from, the value of the PC in ARM processors is 2 instructions (i.e. 8 bytes) beyond the instruction currently being executed.
--
Chris Burrows
CFB Software
Armaide v2.0: LPC2xxx Oberon-07 Development System
http://www.cfbsoftware.com/armaide
>
> Please could you explain to me why the value -0x0FF0 is choosen
> for IRQ processing, in the startup.s file. I have read that for earlier version of VIC used in LPC controllers this value was -0x0120
>
> LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
>
(Actually it is the other way around - 0x0120 is used in the *later*, LPC2300/2400, controllers)
The reason for the two different values is because NXP changed the location of the 'Vector Address Register' when they designed the LPC23xx/LPC24xx MCUs.
If you want to know the significance of the particular values -0x0120 and -0x0FF0 then read on:
In the LDR instruction above the value #-0x0FF0 denotes an offset calculated from the current value of the program counter (PC). Note that the particular LDR instruction you have quoted is located at address 0x18 (the IRQ interrupt vector).
Hence PC, #-0x0FF0 = (PC + 8 -0x0FF0) = (0x18 + 8 - 0x0FF0) = 0xFFFFF030 which is the location of VICVectAddr, the Vector Address register!
Similarly, for the LPC23xx/24xx MCUs:
PC, #-0x0120 = (PC + 8 -0x0120) = (0x18 + 8 -0x0120) = 0xFFFFFF00 which is the location of VICAddress (which is what the Vector Address register is now called).
What this all means is that when an IRQ causes the processor to branch to address 0x18, the PC is then loaded with the value that is contained in the location VICVectAddr / VICAddress. i.e. execution then continues with the interrupt handler whose address has been stored there by the VIC system.
P.S. If you are wondering where the '+ 8' comes from, the value of the PC in ARM processors is 2 instructions (i.e. 8 bytes) beyond the instruction currently being executed.
--
Chris Burrows
CFB Software
Armaide v2.0: LPC2xxx Oberon-07 Development System
http://www.cfbsoftware.com/armaide
