Hi,
i am new to this group in one of my application i have to read/write
external SRAM, i have initialised my emc settings,but being new to the
ARM7 i do not know the routine to access SRAM. can anybody help me in this
regard.
I am using
LPC2468 (NXP)//32bit microcontroller
CY7C1061BV33(cypress)//2 MB external SRAM
Regards
Tripathi Ashutosh
Access to SRAM(Read/Write)
Started by ●June 30, 2009
Reply by ●June 30, 20092009-06-30
Done any programming?
What compiler you are using?
--- In l..., ashutosh@... wrote:
>
> Hi,
> i am new to this group in one of my application i have to read/write
> external SRAM, i have initialised my emc settings,but being new to the
> ARM7 i do not know the routine to access SRAM. can anybody help me in this
> regard.
>
> I am using
> LPC2468 (NXP)//32bit microcontroller
> CY7C1061BV33(cypress)//2 MB external SRAM
>
> Regards
>
> Tripathi Ashutosh
>
What compiler you are using?
--- In l..., ashutosh@... wrote:
>
> Hi,
> i am new to this group in one of my application i have to read/write
> external SRAM, i have initialised my emc settings,but being new to the
> ARM7 i do not know the routine to access SRAM. can anybody help me in this
> regard.
>
> I am using
> LPC2468 (NXP)//32bit microcontroller
> CY7C1061BV33(cypress)//2 MB external SRAM
>
> Regards
>
> Tripathi Ashutosh
>
Reply by ●June 30, 20092009-06-30
> i am using Keil Arm compiler
i have only configuring my emc(external SRAM)
and i am trying to write some data lets say 0xAA on SRAM location
0x80000000.
emc setting is as follows.....
/*pin connect block*/
PINSEL6 = 0x55555555; //D[15:0]/P3[15:0] //if memory can be used as
external boot memory setting for p[15:14]= 10 by cs1.
//in this case it is reserved, do not use.
/*Pin has neither pull up nor pull down*/
PINMODE6 = 0xAAAAAAAA; //mode 10
PINSEL8 = 0x55555555 ;//A[15:0]/P4[15:0]
PINMODE8 = 0xAAAAAAAA ;// mode 10
PINSEL9 = 0x40550055 ;//A[19:16]/P4[19:16 & 31:30 & 27:24]
PINMODE9 = 0xAAAAAAAA ;//mode 10
//Step2: Enable EMC and set EMC parameter
/*Enable EMC power */
PCONP |= 0x800 ;
/* Enable EMC*/
EMC_CTRL = 1 ;
/*PLL is bypassed*/
CCLKCFG = 0x1;
/*AHB slave memory interface & data buffers*/
EMC_CONFIG = ENDIAN_MODE_BIT ;//little endian
EMC_STA_CFG0 = MEM_WDTH |PAGE_MODE |BYTE_LANE_STATE | 1<< 19 ; //32 bits
initially data buffers are dissabled
EMC_STA_WAITWEN0 = 0x2;
EMC_STA_WAITOEN0 = 0x2;
// EMC_STA_WAITRD0 = 0x1F;
EMC_STA_WAITPAGE0 = 0x1F;
EMC_STA_WAITWR0 = 0x1F;
EMC_STA_WAITTURN0 = 0x0F;
EMC_STA_EXT_WAIT = 0x00; // Extended wait time, 16CCLK
EMC_STAT = 0 ;
cReturnValue = WriteToSram() ;
> Done any programming?
>
> What compiler you are using?
>
> --- In l..., ashutosh@... wrote:
>>
>> Hi,
>> i am new to this group in one of my application i have to read/write
>> external SRAM, i have initialised my emc settings,but being new to the
>> ARM7 i do not know the routine to access SRAM. can anybody help me in
>> this
>> regard.
>>
>> I am using
>> LPC2468 (NXP)//32bit microcontroller
>> CY7C1061BV33(cypress)//2 MB external SRAM
>>
>> Regards
>>
>> Tripathi Ashutosh
>
i have only configuring my emc(external SRAM)
and i am trying to write some data lets say 0xAA on SRAM location
0x80000000.
emc setting is as follows.....
/*pin connect block*/
PINSEL6 = 0x55555555; //D[15:0]/P3[15:0] //if memory can be used as
external boot memory setting for p[15:14]= 10 by cs1.
//in this case it is reserved, do not use.
/*Pin has neither pull up nor pull down*/
PINMODE6 = 0xAAAAAAAA; //mode 10
PINSEL8 = 0x55555555 ;//A[15:0]/P4[15:0]
PINMODE8 = 0xAAAAAAAA ;// mode 10
PINSEL9 = 0x40550055 ;//A[19:16]/P4[19:16 & 31:30 & 27:24]
PINMODE9 = 0xAAAAAAAA ;//mode 10
//Step2: Enable EMC and set EMC parameter
/*Enable EMC power */
PCONP |= 0x800 ;
/* Enable EMC*/
EMC_CTRL = 1 ;
/*PLL is bypassed*/
CCLKCFG = 0x1;
/*AHB slave memory interface & data buffers*/
EMC_CONFIG = ENDIAN_MODE_BIT ;//little endian
EMC_STA_CFG0 = MEM_WDTH |PAGE_MODE |BYTE_LANE_STATE | 1<< 19 ; //32 bits
initially data buffers are dissabled
EMC_STA_WAITWEN0 = 0x2;
EMC_STA_WAITOEN0 = 0x2;
// EMC_STA_WAITRD0 = 0x1F;
EMC_STA_WAITPAGE0 = 0x1F;
EMC_STA_WAITWR0 = 0x1F;
EMC_STA_WAITTURN0 = 0x0F;
EMC_STA_EXT_WAIT = 0x00; // Extended wait time, 16CCLK
EMC_STAT = 0 ;
cReturnValue = WriteToSram() ;
> Done any programming?
>
> What compiler you are using?
>
> --- In l..., ashutosh@... wrote:
>>
>> Hi,
>> i am new to this group in one of my application i have to read/write
>> external SRAM, i have initialised my emc settings,but being new to the
>> ARM7 i do not know the routine to access SRAM. can anybody help me in
>> this
>> regard.
>>
>> I am using
>> LPC2468 (NXP)//32bit microcontroller
>> CY7C1061BV33(cypress)//2 MB external SRAM
>>
>> Regards
>>
>> Tripathi Ashutosh
>
Reply by ●June 30, 20092009-06-30
a...@kanalsolutions.com schrieb:
>> i am using Keil Arm compiler
> i have only configuring my emc(external SRAM)
> and i am trying to write some data lets say 0xAA on SRAM location
> 0x80000000.
*(char *)0x80000000 = 0xaa;
--
42Bastian
------------------
Parts of this email are written with invisible ink.
Note: SPAM-only account, direct mail to bs42@...
>> i am using Keil Arm compiler
> i have only configuring my emc(external SRAM)
> and i am trying to write some data lets say 0xAA on SRAM location
> 0x80000000.
*(char *)0x80000000 = 0xaa;
--
42Bastian
------------------
Parts of this email are written with invisible ink.
Note: SPAM-only account, direct mail to bs42@...
Reply by ●June 30, 20092009-06-30
Here's what I use. This was for 32b r/w. The EMC can bit a bit quirky.
As I recall some of the behavior does not quite work as documented, or the
documentation was incomplete, or some regs had to be set in certain order. Some
of the regs had to be set a certain way or it did not work right.
Chris.
// * Setup EMC : External Memory Controller for BUS using SRAM mem map & config
// These timing values produce about 4M*4BMB/Sec BUS data rate
EMC_CTRL = 1; // Enable EMC
EMC_DYN_CFG0 = (1<<14); // DRAM 32b
EMC_DYN_CFG1 = (1<<14); // DRAM 32b
EMC_DYN_CFG2 = (1<<14); // DRAM 32b
EMC_DYN_CFG3 = (1<<14); // DRAM 32b
EMC_DYN_CTRL = 1; // DRAM /CE=1, Shut down Self Refresh
// SRAM config
EMC_STA_CFG0 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG1 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG2 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG3 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
// CCLKrMHz : Tcclk = 14nSec
EMC_STA_WAITWEN0 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN1 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN2 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN3 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITOEN0 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN1 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN2 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN3 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITWR0 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR1 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR2 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR3 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITRD0 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD1 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD2 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD3 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITTURN0 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN1 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN2 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN3 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITPAGE0 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE1 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE2 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE3 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_EXT_WAIT = 0x00; // Static Extended Wait = (n+1) x16 clock cycles.
Chris.
// * Setup EMC : External Memory Controller for BUS using SRAM mem map & config
// These timing values produce about 4M*4BMB/Sec BUS data rate
EMC_CTRL = 1; // Enable EMC
EMC_DYN_CFG0 = (1<<14); // DRAM 32b
EMC_DYN_CFG1 = (1<<14); // DRAM 32b
EMC_DYN_CFG2 = (1<<14); // DRAM 32b
EMC_DYN_CFG3 = (1<<14); // DRAM 32b
EMC_DYN_CTRL = 1; // DRAM /CE=1, Shut down Self Refresh
// SRAM config
EMC_STA_CFG0 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG1 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG2 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
EMC_STA_CFG3 = EMC_STAT_CFG_MEMWID_32 | EMC_STAT_CFG_BYTELANE ; // 32 bit data path, Enable /OE, /WE, Buf
// CCLKrMHz : Tcclk = 14nSec
EMC_STA_WAITWEN0 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN1 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN2 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITWEN3 = 1 ; // (n+1) CCLK delays from /CS to /WR = 28nS
EMC_STA_WAITOEN0 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN1 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN2 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITOEN3 = 2 ; // (n) CCLK delays from /CS to /OE = 14nS
EMC_STA_WAITWR0 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR1 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR2 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITWR3 = 5 ; // (n+2) CCLK delays for write width = 70nS
EMC_STA_WAITRD0 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD1 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD2 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITRD3 = 3 ; // (n+1) CCLK delays for read width = 70nS
EMC_STA_WAITTURN0 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN1 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN2 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITTURN3 = 2 ; // (n+1) CCLK delays for r/w turnaround delay = 42nS
EMC_STA_WAITPAGE0 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE1 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE2 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_WAITPAGE3 = 0x5; // (n+1) CCLK delays for page read = 84nS
EMC_STA_EXT_WAIT = 0x00; // Static Extended Wait = (n+1) x16 clock cycles.
Reply by ●June 30, 20092009-06-30
hi,
am newly working on this board can u guide me to work on LPC 2129 borad...
--- On Tue, 30/6/09, a...@kanalsolutions.com wrote:
From: a...@kanalsolutions.com
Subject: Re: [lpc2000] Re: Access to SRAM(Read/Write)
To: l...
Date: Tuesday, 30 June, 2009, 1:17 PM
> i am using Keil Arm compiler
i have only configuring my emc(external SRAM)
and i am trying to write some data lets say 0xAA on SRAM location
0x80000000.
emc setting is as follows.....
/*pin connect block*/
PINSEL6 = 0x55555555; //D[15:0]/P3[ 15:0] //if memory can be used as
external boot memory setting for p[15:14]= 10 by cs1.
//in this case it is reserved, do not use.
/*Pin has neither pull up nor pull down*/
PINMODE6 = 0xAAAAAAAA; //mode 10
PINSEL8 = 0x55555555 ;//A[15:0]/P4[ 15:0]
PINMODE8 = 0xAAAAAAAA ;// mode 10
PINSEL9 = 0x40550055 ;//A[19:16]/ P4[19:16 & 31:30 & 27:24]
PINMODE9 = 0xAAAAAAAA ;//mode 10
//Step2: Enable EMC and set EMC parameter
/*Enable EMC power */
PCONP |= 0x800 ;
/* Enable EMC*/
EMC_CTRL = 1 ;
/*PLL is bypassed*/
CCLKCFG = 0x1;
/*AHB slave memory interface & data buffers*/
EMC_CONFIG = ENDIAN_MODE_ BIT ;//little endian
EMC_STA_CFG0 = MEM_WDTH |PAGE_MODE |BYTE_LANE_STATE | 1<< 19 ; //32 bits
initially data buffers are dissabled
EMC_STA_WAITWEN0 = 0x2;
EMC_STA_WAITOEN0 = 0x2;
// EMC_STA_WAITRD0 = 0x1F;
EMC_STA_WAITPAGE0 = 0x1F;
EMC_STA_WAITWR0 = 0x1F;
EMC_STA_WAITTURN0 = 0x0F;
EMC_STA_EXT_ WAIT = 0x00; // Extended wait time, 16CCLK
EMC_STAT = 0 ;
cReturnValue = WriteToSram( ) ;
> Done any programming?
>
> What compiler you are using?
>
>
>
> --- In lpc2000@yahoogroups .com, ashutosh@... wrote:
>>
>> Hi,
>> i am new to this group in one of my application i have to read/write
>> external SRAM, i have initialised my emc settings,but being new to the
>> ARM7 i do not know the routine to access SRAM. can anybody help me in
>> this
>> regard.
>>
>> I am using
>> LPC2468 (NXP)//32bit microcontroller
>> CY7C1061BV33( cypress)/ /2 MB external SRAM
>>
>>
>>
>> Regards
>>
>> Tripathi Ashutosh
>>
>
>
>
Love Cricket? Check out live scores, photos, video highlights and more. Click here http://cricket.yahoo.com
am newly working on this board can u guide me to work on LPC 2129 borad...
--- On Tue, 30/6/09, a...@kanalsolutions.com wrote:
From: a...@kanalsolutions.com
Subject: Re: [lpc2000] Re: Access to SRAM(Read/Write)
To: l...
Date: Tuesday, 30 June, 2009, 1:17 PM
> i am using Keil Arm compiler
i have only configuring my emc(external SRAM)
and i am trying to write some data lets say 0xAA on SRAM location
0x80000000.
emc setting is as follows.....
/*pin connect block*/
PINSEL6 = 0x55555555; //D[15:0]/P3[ 15:0] //if memory can be used as
external boot memory setting for p[15:14]= 10 by cs1.
//in this case it is reserved, do not use.
/*Pin has neither pull up nor pull down*/
PINMODE6 = 0xAAAAAAAA; //mode 10
PINSEL8 = 0x55555555 ;//A[15:0]/P4[ 15:0]
PINMODE8 = 0xAAAAAAAA ;// mode 10
PINSEL9 = 0x40550055 ;//A[19:16]/ P4[19:16 & 31:30 & 27:24]
PINMODE9 = 0xAAAAAAAA ;//mode 10
//Step2: Enable EMC and set EMC parameter
/*Enable EMC power */
PCONP |= 0x800 ;
/* Enable EMC*/
EMC_CTRL = 1 ;
/*PLL is bypassed*/
CCLKCFG = 0x1;
/*AHB slave memory interface & data buffers*/
EMC_CONFIG = ENDIAN_MODE_ BIT ;//little endian
EMC_STA_CFG0 = MEM_WDTH |PAGE_MODE |BYTE_LANE_STATE | 1<< 19 ; //32 bits
initially data buffers are dissabled
EMC_STA_WAITWEN0 = 0x2;
EMC_STA_WAITOEN0 = 0x2;
// EMC_STA_WAITRD0 = 0x1F;
EMC_STA_WAITPAGE0 = 0x1F;
EMC_STA_WAITWR0 = 0x1F;
EMC_STA_WAITTURN0 = 0x0F;
EMC_STA_EXT_ WAIT = 0x00; // Extended wait time, 16CCLK
EMC_STAT = 0 ;
cReturnValue = WriteToSram( ) ;
> Done any programming?
>
> What compiler you are using?
>
>
>
> --- In lpc2000@yahoogroups .com, ashutosh@... wrote:
>>
>> Hi,
>> i am new to this group in one of my application i have to read/write
>> external SRAM, i have initialised my emc settings,but being new to the
>> ARM7 i do not know the routine to access SRAM. can anybody help me in
>> this
>> regard.
>>
>> I am using
>> LPC2468 (NXP)//32bit microcontroller
>> CY7C1061BV33( cypress)/ /2 MB external SRAM
>>
>>
>>
>> Regards
>>
>> Tripathi Ashutosh
>>
>
>
>
Love Cricket? Check out live scores, photos, video highlights and more. Click here http://cricket.yahoo.com
Reply by ●July 1, 20092009-07-01
Dear Tripathi,
I had this same problem. After several weeks I received an answer from a
kind member of this forum. This solved my problem. Please see below.
Regards,
Bruce
> Hi,
>
> I finally wrote to NXP , adn after1 month , I got an answer ...
> In fact the EMC controller is the same on LPC2378/88 and LPC2478. But some
registers are not used on LPC23xx.
> And some of the LPC24XX are used but ... not documented !
> There's a register you have to reset to disable theself refreshing of
theRAM (and it's activated on reset)
>
> #define EMC_BASE_ADDR0xFFE08000
> #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR +
0x020)).
>
> After that the Stat register is operating with the correct behavior.
>
> I hope it helps
I had this same problem. After several weeks I received an answer from a
kind member of this forum. This solved my problem. Please see below.
Regards,
Bruce
> Hi,
>
> I finally wrote to NXP , adn after1 month , I got an answer ...
> In fact the EMC controller is the same on LPC2378/88 and LPC2478. But some
registers are not used on LPC23xx.
> And some of the LPC24XX are used but ... not documented !
> There's a register you have to reset to disable theself refreshing of
theRAM (and it's activated on reset)
>
> #define EMC_BASE_ADDR0xFFE08000
> #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR +
0x020)).
>
> After that the Stat register is operating with the correct behavior.
>
> I hope it helps
Reply by ●July 1, 20092009-07-01
Dear members,
I have many queries regarding External SRAM
1)i have a problem to sectorize my sram(2MB)
lets i divide my sram into 256K blocks .
how i do this.
i search for "External SRAM" in help icon of Vision3(Keil Arm).
where i found in the target option there has one setting of "use memory
layout from target dialog" in "Linker" .
and how i can create scatter file.
2)there has an access violation when we write some data lets say 5 on
address 0x80000000,When we debug the program
we select CS0 because its capacity is 16 MB and i am using 2 MB.
Regards,
Tripathi ashutosh
> Dear Tripathi,
>
> I had this same problem. After several weeks I received an answer from a
> kind member of this forum. This solved my problem. Please see below.
>
> Regards,
>
> Bruce
>> Hi,
>>
>> I finally wrote to NXP , adn after1 month , I got an answer ...
>> In fact the EMC controller is the same on LPC2378/88 and LPC2478. But
>> some
> registers are not used on LPC23xx.
>> And some of the LPC24XX are used but ... not documented !
>> There's a register you have to reset to disable theself refreshing of
> theRAM (and it's activated on reset)
>>
>> #define EMC_BASE_ADDR0xFFE08000
>> #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR +
> 0x020)).
>>
>> After that the Stat register is operating with the correct behavior.
>>
>> I hope it helps
I have many queries regarding External SRAM
1)i have a problem to sectorize my sram(2MB)
lets i divide my sram into 256K blocks .
how i do this.
i search for "External SRAM" in help icon of Vision3(Keil Arm).
where i found in the target option there has one setting of "use memory
layout from target dialog" in "Linker" .
and how i can create scatter file.
2)there has an access violation when we write some data lets say 5 on
address 0x80000000,When we debug the program
we select CS0 because its capacity is 16 MB and i am using 2 MB.
Regards,
Tripathi ashutosh
> Dear Tripathi,
>
> I had this same problem. After several weeks I received an answer from a
> kind member of this forum. This solved my problem. Please see below.
>
> Regards,
>
> Bruce
>> Hi,
>>
>> I finally wrote to NXP , adn after1 month , I got an answer ...
>> In fact the EMC controller is the same on LPC2378/88 and LPC2478. But
>> some
> registers are not used on LPC23xx.
>> And some of the LPC24XX are used but ... not documented !
>> There's a register you have to reset to disable theself refreshing of
> theRAM (and it's activated on reset)
>>
>> #define EMC_BASE_ADDR0xFFE08000
>> #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR +
> 0x020)).
>>
>> After that the Stat register is operating with the correct behavior.
>>
>> I hope it helps
