I've been looking at a variety of schematics for an LPC2103 board I was
working on, and it I've seen RTCK on the JTAG port pulled both high and low
on different schematics. I pulled it high on my board (following an 2103 Olimex
board I use), but I'm not really sure if I made the correct choice now and
the 2103 datasheet doesn't seem to be much help. All I found was:
"Returned test clock output: Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up."
Can anyone offer a concrete answer on whether RTCK should be pulled high or low
for the 2103?
RTCK high or low on LPC2103?
Started by ●September 6, 2009
Reply by ●September 6, 20092009-09-06
--- In l..., "kevin_townsend2" wrote:
>
> I've been looking at a variety of schematics for an LPC2103 board I was working on, and it I've seen RTCK on the JTAG port pulled both high and low on different schematics. I pulled it high on my board (following an 2103 Olimex board I use), but I'm not really sure if I made the correct choice now and the 2103 datasheet doesn't seem to be much help. All I found was:
>
> "Returned test clock output: Extra signal added to the JTAG
> port. Assists debugger synchronization when processor
> frequency varies. Bidirectional pin with internal pull-up."
>
> Can anyone offer a concrete answer on whether RTCK should be pulled high or low for the 2103?
>
Get the LPC2103 User Manual. Look in chapter 20 EmbeddedICE logic, section 5 Reset State of Multiplexed Pins (page 262 of Rev. 4 13 May 2009). Your answer is there.
http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
TC
>
> I've been looking at a variety of schematics for an LPC2103 board I was working on, and it I've seen RTCK on the JTAG port pulled both high and low on different schematics. I pulled it high on my board (following an 2103 Olimex board I use), but I'm not really sure if I made the correct choice now and the 2103 datasheet doesn't seem to be much help. All I found was:
>
> "Returned test clock output: Extra signal added to the JTAG
> port. Assists debugger synchronization when processor
> frequency varies. Bidirectional pin with internal pull-up."
>
> Can anyone offer a concrete answer on whether RTCK should be pulled high or low for the 2103?
>
Get the LPC2103 User Manual. Look in chapter 20 EmbeddedICE logic, section 5 Reset State of Multiplexed Pins (page 262 of Rev. 4 13 May 2009). Your answer is there.
http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
TC
Reply by ●September 6, 20092009-09-06
> Get the LPC2103 User Manual. Look in chapter 20
EmbeddedICE logic, section 5 Reset State of Multiplexed Pins (page 262 of Rev. 4
13 May 2009). Your answer is there.
>
> http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
Thanks ... I thought pulled high was correct, and was hoping I didn't screw something up since I sent the gerber's out this morning for manufacturing. I've typically pulled RTCK low on other chips like the 2148. Is the need to pull it high specific to the 2101/2/3 family?
>
> http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
Thanks ... I thought pulled high was correct, and was hoping I didn't screw something up since I sent the gerber's out this morning for manufacturing. I've typically pulled RTCK low on other chips like the 2148. Is the need to pull it high specific to the 2101/2/3 family?
Reply by ●September 6, 20092009-09-06
--- In l..., "kevin_townsend2" wrote:
>
> > Get the LPC2103 User Manual. Look in chapter 20 EmbeddedICE logic, section 5 Reset State of Multiplexed Pins (page 262 of Rev. 4 13 May 2009). Your answer is there.
> >
> > http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
>
> Thanks ... I thought pulled high was correct, and was hoping I didn't screw something up since I sent the gerber's out this morning for manufacturing. I've typically pulled RTCK low on other chips like the 2148. Is the need to pull it high specific to the 2101/2/3 family?
>
For the 2148 the User's Manual says:
"On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
Kevin.
>
> > Get the LPC2103 User Manual. Look in chapter 20 EmbeddedICE logic, section 5 Reset State of Multiplexed Pins (page 262 of Rev. 4 13 May 2009). Your answer is there.
> >
> > http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2101.lpc2102.lpc2103.pdf
>
> Thanks ... I thought pulled high was correct, and was hoping I didn't screw something up since I sent the gerber's out this morning for manufacturing. I've typically pulled RTCK low on other chips like the 2148. Is the need to pull it high specific to the 2101/2/3 family?
>
For the 2148 the User's Manual says:
"On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
Kevin.
Reply by ●September 6, 20092009-09-06
--- In l..., "kevin_townsend2" wrote:
> For the 2148 the User's Manual says:
>
> "On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
>
> Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
>
> Kevin.
>
I think it is the same and you are misunderstanding the text.
I'm pretty sure that you will find elsewhere in the documentation that RTCK is pulled-up internally on both the LPC210x and the LPC214x. If the pin is left unconnected, or is externally pulled-up, or is externally driven high when reset is released then the pins come out of reset as GPIO pins.
If the RTCK pin is externally pulled-low, or externally driven low when reset is released then the pins come of reset as JTAG pins.
TC
> For the 2148 the User's Manual says:
>
> "On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
>
> Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
>
> Kevin.
>
I think it is the same and you are misunderstanding the text.
I'm pretty sure that you will find elsewhere in the documentation that RTCK is pulled-up internally on both the LPC210x and the LPC214x. If the pin is left unconnected, or is externally pulled-up, or is externally driven high when reset is released then the pins come out of reset as GPIO pins.
If the RTCK pin is externally pulled-low, or externally driven low when reset is released then the pins come of reset as JTAG pins.
TC
Reply by ●September 6, 20092009-09-06
my Olimex boards have an external pull-up on this pin. I use simple JTAG.
--- In l..., "tcirobot" wrote:
>
> --- In l..., "kevin_townsend2" wrote:
> > For the 2148 the User's Manual says:
> >
> > "On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
> >
> > Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
> >
> > Kevin.
> >
>
> I think it is the same and you are misunderstanding the text.
>
> I'm pretty sure that you will find elsewhere in the documentation that RTCK is pulled-up internally on both the LPC210x and the LPC214x. If the pin is left unconnected, or is externally pulled-up, or is externally driven high when reset is released then the pins come out of reset as GPIO pins.
>
> If the RTCK pin is externally pulled-low, or externally driven low when reset is released then the pins come of reset as JTAG pins.
>
> TC
>
--- In l..., "tcirobot" wrote:
>
> --- In l..., "kevin_townsend2" wrote:
> > For the 2148 the User's Manual says:
> >
> > "On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kdepending on the external JTAG circuitry) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset."
> >
> > Meaning on this chip it needs to be pulled low. I would have expected the chips to have the same configuration, but I'll obviously have to read up on the JTAG layout before sending any 21xx boards off for manufacturing if it varies between models even in the same family (2103 = RTCK High, 2148 = RTCK low, etc).
> >
> > Kevin.
> >
>
> I think it is the same and you are misunderstanding the text.
>
> I'm pretty sure that you will find elsewhere in the documentation that RTCK is pulled-up internally on both the LPC210x and the LPC214x. If the pin is left unconnected, or is externally pulled-up, or is externally driven high when reset is released then the pins come out of reset as GPIO pins.
>
> If the RTCK pin is externally pulled-low, or externally driven low when reset is released then the pins come of reset as JTAG pins.
>
> TC
>
Reply by ●September 7, 20092009-09-07
--- In l..., "stevech11" wrote:
>
> my Olimex boards have an external pull-up on this pin. I use simple JTAG.
Even Olimex isn't consistent on this. Their 2103 header board has it pulled high, but their 2148 board has it pulled low.
2103:
http://www.olimex.com/dev/images/lpc-h2103-sch.gif
2148:
http://www.olimex.com/dev/images/ARM/LPC/LPC-P2148-REV-D-sch.gif
The jumper is in place on RTCK by default meaning when it is pulled down it defaults to JTAG (at least on my board :). If I remove the jumper and leave it floating I believe it defaults to GPIO.
Kevin.
>
> my Olimex boards have an external pull-up on this pin. I use simple JTAG.
Even Olimex isn't consistent on this. Their 2103 header board has it pulled high, but their 2148 board has it pulled low.
2103:
http://www.olimex.com/dev/images/lpc-h2103-sch.gif
2148:
http://www.olimex.com/dev/images/ARM/LPC/LPC-P2148-REV-D-sch.gif
The jumper is in place on RTCK by default meaning when it is pulled down it defaults to JTAG (at least on my board :). If I remove the jumper and leave it floating I believe it defaults to GPIO.
Kevin.
