Hi

Has anyone got initialisation code/parameters to initiate the use of the external RAM on the OLIMEX LPC-2478-STK?

Regards

Jean-Jacques

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--- In l..., "jdauchot" wrote:
>
> Hi
>
> Has anyone got initialisation code/parameters to initiate the use of the external RAM on the OLIMEX LPC-2478-STK?
>
>
>
> Regards
>
>
>
> Jean-Jacques
>
http://www.nxp.com/acrobat_download/applicationnotes/AN10771_1.pdf

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You will also need this for testing.
unsigned int SDRAM_Test (void)
{
UNS_32 i;

// 32 bits access
for (i = 0; i < 0x400000; i+=sizeof(unsigned int))
{
*(unsigned int *)((unsigned int )&SDRAM_BASE_ADDR+(unsigned int )i) = i;

}
for (i = 0; i < 0x400000; i+=sizeof(unsigned int ))
{
if (*(unsigned int *)((unsigned int )&SDRAM_BASE_ADDR+(unsigned int )i)
!= i)
{
printf("Verification error on address :
0x%x\n",(UNS_32)&SDRAM_BASE_ADDR+i);
return(FALSE);
}
}
// 16 bits access
for (i = 0; i < 0x10000; i+=sizeof(unsigned short))
{
*(unsigned short*)((unsigned int)&SDRAM_BASE_ADDR+i) = i;
}
for (i = 0; i < 0x10000; i+=sizeof(unsigned short))
{
if (*(unsigned short*)((unsigned int)&SDRAM_BASE_ADDR+i) != i)
{
printf("Verification error on address :
0x%x\n",(UNS_32)&SDRAM_BASE_ADDR+i);
return(FALSE);
}
}
// 8 bits access
for ( i = 0; i < 0x100; i+=sizeof(unsigned char))
{
*(unsigned char*)((unsigned int)&SDRAM_BASE_ADDR+i) = i;
}
for (i = 0; i < 0x100; i+=sizeof(unsigned char))
{
if (*(unsigned char*)((unsigned int)&SDRAM_BASE_ADDR+i) != i)
{
printf("Verification error on address :
0x%x\n",(UNS_32)&SDRAM_BASE_ADDR+i);
return(FALSE);
}
}
return(TRUE);
}
2009/10/3 Felipe de A N L

> Yes... now you own me your life, hehe.
>
> you will have to fix the typedefs,
> UNS_32 means unsigned int.. it is understandable.
>
> /*************************************************************************
> * Function Name: SDRAM_Init
> * Parameters: none
> *
> * Return: none
> *
> * Description: SDRAM controller and memory init
> *
> *************************************************************************/
>
> void SDRAM_Init (void)
> {
> UNS_32 i;
> volatile UNS_64 Dummy;
>
> // Assign pins to SDRAM controller
> PINSEL5 &= 0x00FCFCC0;
> PINSEL5 |= 0x55010115;
> PINMODE5&= 0x00FCFCC0;
> PINMODE5|= 0xAA02022A;
> PINSEL6 |= 0x55555555;
> PINMODE6 |= 0xAAAAAAAA;
> PINSEL7 |= 0x55555555;
> PINMODE7 |= 0xAAAAAAAA;
> PINSEL8 &= 0xC0000000;
> PINSEL8 |= 0x15555555;
> PINMODE8&= 0xC0000000;
> PINMODE8|= 0x2AAAAAAA;
> PINSEL9 &= 0xFFF3FFFF;
> PINSEL9 |= 0x00040000;
> PINMODE9&= 0xFFF3FFFF;
> PINMODE9|= 0x00080000;
>
> // Init SDRAM controller
> // Enable EMC clock
> PCONP |= 0x800;
> EMC_CTRL = 1;
> EMC_DYN_RD_CFG = 1;
> EMC_DYN_RASCAS0&=0xFFFFFFFF; EMC_DYN_RASCAS0|=0x300; //CAS latency=3
> EMC_DYN_RASCAS0|=0x3; // RAS latency(active to read/write delay)=3
> /*EMC_DYN_RP = P2C(SDRAM_TRP);
> EMC_DYN_RAS = P2C(SDRAM_TRAS);
> EMC_DYN_SREX = P2C(SDRAM_TXSR);
> EMC_DYN_APR = SDRAM_TAPR;
> EMC_DYN_DAL = SDRAM_TDAL+P2C(SDRAM_TRP);
> EMC_DYN_WR = SDRAM_TWR;
> EMC_DYN_RC = P2C(SDRAM_TRC);
> EMC_DYN_RFC = P2C(SDRAM_TRFC);
> EMC_DYN_XSR = P2C(SDRAM_TXSR);
> EMC_DYN_RRD = P2C(SDRAM_TRRD);
> EMC_DYN_MRD = SDRAM_TMRD; */
>
> EMC_DYN_RP= P2C(SDRAM_TRP);
> EMC_DYN_RAS = P2C(SDRAM_TRAS);
> EMC_DYN_SREX = SDRAM_TXSR;
> EMC_DYN_APR = SDRAM_TAPR;
> EMC_DYN_DAL =SDRAM_TDAL ;
> EMC_DYN_WR = SDRAM_TWR;
> EMC_DYN_RC = P2C(SDRAM_TRC);
> EMC_DYN_RFC = P2C(SDRAM_TRFC);
> EMC_DYN_XSR = SDRAM_TXSR;
> EMC_DYN_RRD = P2C(SDRAM_TRRD);
> EMC_DYN_MRD = SDRAM_TMRD;
>
> EMC_DYN_CFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
> //EMC_DYN_CFG0 = (1u << 14) | (0u << 12) | (3u << 9) | (1u <<
> 7); // 13 row, 9 - col, SDRAM
> // JEDEC General SDRAM Initialization Sequence
> // DELAY to allow power and clocks to stabilize ~100 us
> // NOP
> EMC_DYN_CTRL = 0x0183;
> for(i = 200*30; i;i--);
> // PALL
> EMC_DYN_CTRL |= 0x100; EMC_DYN_CTRL &= 0xFFFFFF7F;
> EMC_DYN_RFSH = 1;
> for(i= 128; i; --i); // > 128 clk
> EMC_DYN_RFSH = P2C(SDRAM_REFRESH) >> 4;
> // COMM
> EMC_DYN_CTRL|=0x80; EMC_DYN_CTRL&=0xFFFFFEFF;
> // Burst 8, Sequential, CAS-2
> Dummy = *(volatile unsigned int *)((UNS_32)&SDRAM_BASE_ADDR + (0x33UL <<
> (12)));
>
> //SHIFT_HIGH_PERFORMANCE = COL + TBW + BANK, where
> //COL=# of column bits (here: 9)
> //TBW=total bus width, 1 bits, 22 bits (here: 2)
> //BANK=# of bank select bits (here: 2)
> // --Formula courtesy of Rolf Meeser
> // Burst 4, Sequential, CAS-3
> //volatile unsigned long Dummy = *(volatile unsigned int
> *)((Int32U)SDRAM_BASE_ADDR + (0x32UL << (13)));
> // NORM
> EMC_DYN_CTRL = 0x0000; //Issue SDRAM norm command ; CLKOUT stop;All
> clock enables low
> EMC_DYN_CFG0|=0x80000; //Buffer enabled for accesses to DCS0 chip
>
> for(i = 10000; i;i--);
> }
> 2009/10/2 Donald H
>>
>> --- In l... , "jdauchot"
>> wrote:
>> >
>> > Hi
>> >
>> > Has anyone got initialisation code/parameters to initiate the use of the
>> external RAM on the OLIMEX LPC-2478-STK?
>> >
>> >
>> >
>> > Regards
>> >
>> >
>> >
>> > Jean-Jacques
>> >
>> http://www.nxp.com/acrobat_download/applicationnotes/AN10771_1.pdf
>>
>>
>>


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Yes... now you own me your life, hehe.

you will have to fix the typedefs,
UNS_32 means unsigned int.. it is understandable.

/*************************************************************************
* Function Name: SDRAM_Init
* Parameters: none
*
* Return: none
*
* Description: SDRAM controller and memory init
*
*************************************************************************/
void SDRAM_Init (void)
{
UNS_32 i;
volatile UNS_64 Dummy;

// Assign pins to SDRAM controller
PINSEL5 &= 0x00FCFCC0;
PINSEL5 |= 0x55010115;
PINMODE5&= 0x00FCFCC0;
PINMODE5|= 0xAA02022A;
PINSEL6 |= 0x55555555;
PINMODE6 |= 0xAAAAAAAA;
PINSEL7 |= 0x55555555;
PINMODE7 |= 0xAAAAAAAA;
PINSEL8 &= 0xC0000000;
PINSEL8 |= 0x15555555;
PINMODE8&= 0xC0000000;
PINMODE8|= 0x2AAAAAAA;
PINSEL9 &= 0xFFF3FFFF;
PINSEL9 |= 0x00040000;
PINMODE9&= 0xFFF3FFFF;
PINMODE9|= 0x00080000;

// Init SDRAM controller
// Enable EMC clock
PCONP |= 0x800;
EMC_CTRL = 1;
EMC_DYN_RD_CFG = 1;
EMC_DYN_RASCAS0&=0xFFFFFFFF; EMC_DYN_RASCAS0|=0x300; //CAS latency=3
EMC_DYN_RASCAS0|=0x3; // RAS latency(active to read/write delay)=3
/*EMC_DYN_RP = P2C(SDRAM_TRP);
EMC_DYN_RAS = P2C(SDRAM_TRAS);
EMC_DYN_SREX = P2C(SDRAM_TXSR);
EMC_DYN_APR = SDRAM_TAPR;
EMC_DYN_DAL = SDRAM_TDAL+P2C(SDRAM_TRP);
EMC_DYN_WR = SDRAM_TWR;
EMC_DYN_RC = P2C(SDRAM_TRC);
EMC_DYN_RFC = P2C(SDRAM_TRFC);
EMC_DYN_XSR = P2C(SDRAM_TXSR);
EMC_DYN_RRD = P2C(SDRAM_TRRD);
EMC_DYN_MRD = SDRAM_TMRD; */

EMC_DYN_RP= P2C(SDRAM_TRP);
EMC_DYN_RAS = P2C(SDRAM_TRAS);
EMC_DYN_SREX = SDRAM_TXSR;
EMC_DYN_APR = SDRAM_TAPR;
EMC_DYN_DAL =SDRAM_TDAL ;
EMC_DYN_WR = SDRAM_TWR;
EMC_DYN_RC = P2C(SDRAM_TRC);
EMC_DYN_RFC = P2C(SDRAM_TRFC);
EMC_DYN_XSR = SDRAM_TXSR;
EMC_DYN_RRD = P2C(SDRAM_TRRD);
EMC_DYN_MRD = SDRAM_TMRD;

EMC_DYN_CFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
//EMC_DYN_CFG0 = (1u << 14) | (0u << 12) | (3u << 9) | (1u << 7);
// 13 row, 9 - col, SDRAM
// JEDEC General SDRAM Initialization Sequence
// DELAY to allow power and clocks to stabilize ~100 us
// NOP
EMC_DYN_CTRL = 0x0183;
for(i = 200*30; i;i--);
// PALL
EMC_DYN_CTRL |= 0x100; EMC_DYN_CTRL &= 0xFFFFFF7F;
EMC_DYN_RFSH = 1;
for(i= 128; i; --i); // > 128 clk
EMC_DYN_RFSH = P2C(SDRAM_REFRESH) >> 4;
// COMM
EMC_DYN_CTRL|=0x80; EMC_DYN_CTRL&=0xFFFFFEFF;
// Burst 8, Sequential, CAS-2
Dummy = *(volatile unsigned int *)((UNS_32)&SDRAM_BASE_ADDR + (0x33UL <<
(12)));

//SHIFT_HIGH_PERFORMANCE = COL + TBW + BANK, where
//COL=# of column bits (here: 9)
//TBW=total bus width, 1 bits, 22 bits (here: 2)
//BANK=# of bank select bits (here: 2)
// --Formula courtesy of Rolf Meeser
// Burst 4, Sequential, CAS-3
//volatile unsigned long Dummy = *(volatile unsigned int
*)((Int32U)SDRAM_BASE_ADDR + (0x32UL << (13)));
// NORM
EMC_DYN_CTRL = 0x0000; //Issue SDRAM norm command ; CLKOUT stop;All clock
enables low
EMC_DYN_CFG0|=0x80000; //Buffer enabled for accesses to DCS0 chip

for(i = 10000; i;i--);
}
2009/10/2 Donald H

> --- In l... , "jdauchot"
> wrote:
> >
> > Hi
> >
> > Has anyone got initialisation code/parameters to initiate the use of the
> external RAM on the OLIMEX LPC-2478-STK?
> >
> >
> >
> > Regards
> >
> >
> >
> > Jean-Jacques
> >
> http://www.nxp.com/acrobat_download/applicationnotes/AN10771_1.pdf
>
>
>


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