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LPC1678 ADC input impedance

Started by nave...@yahoo.com August 25, 2010
On 8/26/2010 11:11 AM, n...@yahoo.com wrote:
> Thanks for all of your inputs which are very helpful. It seems like
> we have to add an opamp buffer to overcome the low ADC input
> impedance. We are used to the Atmel AVR series which have an input
> impedance of 100Mohms so doesn't require any additional buffering.

Really? From an AVR datasheet "The ADC is optimized for analog signals
with an output impedance of approximately 10 kΩ or less." What one were
you using with 100MOhm input impedance?

> Using an opamp buffer means we also need to add a negative voltage
> generator to ensure true rail to rail performance for input signals.

Make sure it can drive a capacitive load. Check Analog devices they
have a good app note somewhere on the op-amp circuitry required to drive
A/Ds well.

> On another note, since the 8 ADC channels provided by the LPC1768
> aren't enough for our application, we want to use several external
> analog mux such as the CD4051. It would seem that the best
> configuration would be to have the analog input going to the mux
> first and a single opamp between the mux output& LPC1768's ADC. Or
> would it be better to have an opamp for every input and put the mux
> between opamp output and the LPC1768's ADC? Does this make any
> difference?

There are advantages to both. I'd usually want to buffer each signal so
you don't get discontinuities on the op-amp input and avoid cross
coupling the signals. OTOH doing that means the op-amps have to handle
switching loads.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."

An Engineer's Guide to the LPC2100 Series

--- In l..., David Smead wrote:

> On Thu, Aug 26, 2010 at 8:11 AM, wrote:
>
> >
> >
> > Thanks for all of your inputs which are very helpful. It seems like we have
> > to add an opamp buffer to overcome the low ADC input impedance. We are used
> Using an opamp buffer means we also need
> > to add a negative voltage generator to ensure true rail to rail performance
> > for input signals.
> >
> > On another note, since the 8 ADC channels provided by the LPC1768 aren't
> > enough for our application, we want to use several external analog mux such
> > as the CD4051. It would seem that the best configuration would be to have
> > the analog input going to the mux first and a single opamp between the mux
> > output & LPC1768's ADC. Or would it be better to have an opamp for every
> > input and put the mux between opamp output and the LPC1768's ADC? Does this
> > make any difference?
> >
>
TI makes a line of rail-to-rail input & output opamps. Again, see chapter 4 of Op Amps For Everyone.

You can always rescale and offset your way out of the corners and still use a single supply opamp. Assuming 0-3V operation, just rescale to 0-2V and add 0.5V Now you are working between 0.5V and 2.5V. You can pick better numbers; perhaps 0.1V out of the corners is adequate.

Richard

--- In l..., Robert Adsett wrote:
>
> On 8/26/2010 3:49 PM, bobtransformer wrote:
> > --- In l..., Robert Adsett
> > wrote:
> >> I've not seen a multiplexed uP A/D input that is anywhere near the
> >> MOhm range. The inputs should always have an RC filter in front for
> >> two reasons. 1 - To filter out high frequency signals (especially
> >> impulse). Note this is true even for sources that are supposedly
> >> bandwidth limited. 2 - To provide a low impedance source of charge
> >> that will allow the S/H cap to charge or discharge without
> >> affecting the voltage level significantly.
> >>
> >
> >
> >
> > They very well could be using a sample and hold, but it shouldn't be
> > necessary if the mux stays on that channel for the entire conversion
> > cycle.
>
> A sample and hold is part of any multiplexed uP A/D I have ever seen.
> It's unavoidable. Even staying on the same channel doesn't avoid it,
> the circuitry will still do a sample and hold. In some systems the
> behaviour is completely fixed, in others you have some control over
> timing such as the sampling time. In no case that I'm aware of can you
> turn it off and you would never want to.
I would hope they use a S/H and that it would hold soon after start conversion is applied. Since I haven't seen S/H in their drawings, I just won't bet my life on it.

You're most likely right though.

boB

>
> Robert
>
> --
> http://www.aeolusdevelopment.com/
>
> From the Divided by a Common Language File (Edited to protect the guilty)
> ME - "I'd like to get Price and delivery for connector Part # XXXXX"
> Dist./Rep - "$X.XX Lead time 37 days"
> ME - "Anything we can do about lead time? 37 days seems a bit high."
> Dist./Rep - "that is the lead time given because our stock is live....
> we currently have stock."
>

--- In l..., "bobtransformer" wrote:
>
> --- In l..., Robert Adsett wrote:
> >
> > On 8/26/2010 3:49 PM, bobtransformer wrote:
> > > --- In l..., Robert Adsett
> > > wrote:
> > >> I've not seen a multiplexed uP A/D input that is anywhere near the
> > >> MOhm range. The inputs should always have an RC filter in front for
> > >> two reasons. 1 - To filter out high frequency signals (especially
> > >> impulse). Note this is true even for sources that are supposedly
> > >> bandwidth limited. 2 - To provide a low impedance source of charge
> > >> that will allow the S/H cap to charge or discharge without
> > >> affecting the voltage level significantly.
> > >>
> > >
> > >
> > >
> > > They very well could be using a sample and hold, but it shouldn't be
> > > necessary if the mux stays on that channel for the entire conversion
> > > cycle.
> >
> > A sample and hold is part of any multiplexed uP A/D I have ever seen.
> > It's unavoidable. Even staying on the same channel doesn't avoid it,
> > the circuitry will still do a sample and hold. In some systems the
> > behaviour is completely fixed, in others you have some control over
> > timing such as the sampling time. In no case that I'm aware of can you
> > turn it off and you would never want to.
> I would hope they use a S/H and that it would hold soon after start conversion is applied. Since I haven't seen S/H in their drawings, I just won't bet my life on it.
>
> You're most likely right though.
>
> boB
>

I'm not sure how applicable this is for ALL NXP processors, but you got me curious and I found this thread regarding the LPC1343...

http://knowledgebase.nxp.com/showthread.php?tC5

(in part)

Find all posts by mhjerde
Old 06-04-2010, 04:34 PM
NXP_Europe NXP_Europe is offline
Support Team member

Join Date: Dec 2009
Location: Nijmegen, The Netherlands
Posts: 55

Hi Morten,
Nope we have a track and hold no sample and hold. So it means that the signal should be present and stable for at least 2,44 us.

Kind regards,
__________________
- NXP European team -

boB

>
> >
> > Robert
> >
> > --
> > http://www.aeolusdevelopment.com/
> >
> > From the Divided by a Common Language File (Edited to protect the guilty)
> > ME - "I'd like to get Price and delivery for connector Part # XXXXX"
> > Dist./Rep - "$X.XX Lead time 37 days"
> > ME - "Anything we can do about lead time? 37 days seems a bit high."
> > Dist./Rep - "that is the lead time given because our stock is live....
> > we currently have stock."
>

On 8/27/2010 12:15 AM, bobtransformer wrote:
> I'm not sure how applicable this is for ALL NXP processors, but you
> got me curious and I found this thread regarding the LPC1343...
>
> http://knowledgebase.nxp.com/showthread.php?tC5
>
> (in part)
>
> Find all posts by mhjerde Old 06-04-2010, 04:34 PM NXP_Europe
> NXP_Europe is offline Support Team member Join Date: Dec 2009
> Location: Nijmegen, The Netherlands Posts: 55
>
> Hi Morten, Nope we have a track and hold no sample and hold. So it
> means that the signal should be present and stable for at least 2,44
> us.

Um, track and hold is a synonym for sample and hold.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."
On 8/27/2010 12:07 AM, bobtransformer wrote:
> I would hope they use a S/H and that it would hold soon after start
> conversion is applied. Since I haven't seen S/H in their drawings, I
> just won't bet my life on it.
>

Take a look at figure 26 and table 20 of the LPC1768 data sheet (
http://ics.nxp.com/products/lpc1000/datasheet/lpc1763.lpc1764.lpc1765.lpc1766.lpc1767.lpc1768.lpc1769.pdf
). The capacitor C3 is the sampling capacitor. It's immediately after
the switch Ri2, a very strong indication of the presence of a S&H
circuit. Even if it's not explicit.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."
--- In l..., Robert Adsett wrote:
>
> On 8/27/2010 12:07 AM, bobtransformer wrote:
> > I would hope they use a S/H and that it would hold soon after start
> > conversion is applied. Since I haven't seen S/H in their drawings, I
> > just won't bet my life on it.
> > Take a look at figure 26 and table 20 of the LPC1768 data sheet (
> http://ics.nxp.com/products/lpc1000/datasheet/lpc1763.lpc1764.lpc1765.lpc1766.lpc1767.lpc1768.lpc1769.pdf
> ). The capacitor C3 is the sampling capacitor. It's immediately after
> the switch Ri2, a very strong indication of the presence of a S&H
> circuit. Even if it's not explicit.
>
> Robert

That's a good find, Robert. Also, sorta answers the question about what to expect for input impedance.

Thanks,
boB

>
> --
> http://www.aeolusdevelopment.com/
>
> From the Divided by a Common Language File (Edited to protect the guilty)
> ME - "I'd like to get Price and delivery for connector Part # XXXXX"
> Dist./Rep - "$X.XX Lead time 37 days"
> ME - "Anything we can do about lead time? 37 days seems a bit high."
> Dist./Rep - "that is the lead time given because our stock is live....
> we currently have stock."
>

--- In l..., "bobtransformer" wrote:
>
> --- In l..., Robert Adsett wrote:
> >
> > On 8/27/2010 12:07 AM, bobtransformer wrote:
> > > I would hope they use a S/H and that it would hold soon after start
> > > conversion is applied. Since I haven't seen S/H in their drawings, I
> > > just won't bet my life on it.
> > >
> >
> > Take a look at figure 26 and table 20 of the LPC1768 data sheet (
> > http://ics.nxp.com/products/lpc1000/datasheet/lpc1763.lpc1764.lpc1765.lpc1766.lpc1767.lpc1768.lpc1769.pdf
> > ). The capacitor C3 is the sampling capacitor. It's immediately after
> > the switch Ri2, a very strong indication of the presence of a S&H
> > circuit. Even if it's not explicit.
> >
> > Robert
>
> That's a good find, Robert. Also, sorta answers the question about what to expect for input impedance.
It would be more informative though, if they showed the timing of the switches and conversion process. That could influence impedance somewhat as well as T&H vs S&H definitions. I've never had a problem with input impedance as far as I know... Even using a 74HC4051 on one of the inputs. No Op Amps. But R-C LPF of course at the very least.
boB

>
> Thanks,
> boB
> >
> > --
> > http://www.aeolusdevelopment.com/
> >
> > From the Divided by a Common Language File (Edited to protect the guilty)
> > ME - "I'd like to get Price and delivery for connector Part # XXXXX"
> > Dist./Rep - "$X.XX Lead time 37 days"
> > ME - "Anything we can do about lead time? 37 days seems a bit high."
> > Dist./Rep - "that is the lead time given because our stock is live....
> > we currently have stock."
>

On 8/28/2010 1:07 AM, bobtransformer wrote:
>> That's a good find, Robert. Also, sorta answers the question
>> about what to expect for input impedance.
> It would be more informative though, if they showed the timing of the
> switches and conversion process. That could influence impedance
> somewhat as well as T&H vs S&H definitions. I've never had a problem
> with input impedance as far as I know... Even using a 74HC4051 on
> one of the inputs. No Op Amps. But R-C LPF of course at the very
> least.

I've always used an RC just before the A/D as well. Even with an Op-amp
before hand. If only as a final Nyquist filter. I had an experience
with induced glitches that lead that to being an iron-clad rule. It's
cheap insurance.

And unless you have a very large sampling cap or a very small filter cap
on the RC the filter cap swamps the sampling cap basically eliminating
worries about input impedance (the input impedance is the filter cap's
impedance).

This T&H vs S&H distinction that some seem to be maintaining I find odd.
I've always been taught that they were synonyms and the references
I've seen that distinguish between them seem to rely on sampling time, a
very odd place to make a distinction and which seems a distinction
without a difference.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."

Memfault Beyond the Launch