hello,
i want to use an external SRAM (size 1M)with LPC2294 ?
it have a problem if i use SRAM 8bit ?
if i choose SRAM with access time 55ns , it have any problem ?
thank you
external SRAM with LPC2294
Started by ●May 18, 2011
Reply by ●May 20, 20112011-05-20
--- In l..., "zied130187" wrote:
>
> hello,
>
> i want to use an external SRAM (size 1M) with LPC2294 ?
>
> it have a problem if i use SRAM 8bit ?
>
> if i choose SRAM with access time 55ns , it have any problem ?
>
> thank you
>
any idea please ?
why the address of SRAM 1M in olimex LPC2294 is 0x81000000 ?
>
> hello,
>
> i want to use an external SRAM (size 1M) with LPC2294 ?
>
> it have a problem if i use SRAM 8bit ?
>
> if i choose SRAM with access time 55ns , it have any problem ?
>
> thank you
>
any idea please ?
why the address of SRAM 1M in olimex LPC2294 is 0x81000000 ?
Reply by ●May 20, 20112011-05-20
Hi,
I can't, of course, speak for anyone other than myself, but, I do have a bit of
a feel for the nature of this group. Most likely nobody has responded for a
couple of reasons. First, this tends to be more of a software-oriented group
and you were asking a hardware design oriented question. The second reason,
however, is probably the more important reason since I know there are any number
of people out there who could answer your questions. Simply put, they are,
quite reasonably, not inclined to do more work on your problem than you appear
to have done yourself. To avoid that perception, you should start by visiting
the NXP site and read the relevant sections of the Datasheet and User Manual.
From the Datasheet: (Rev. 7)
6.7 External memory controller
The external Static Memory Controller is a module which provides an interface
between
the system bus and external (off-chip) memory devices. It provides support for
up to four
independently configurable memory banks (16 MB each with byte lane enable
control)
simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
EPROM,
burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
I haven't looked at the Olimex board, but, presumably it is accessing the
SRAM with CS1 which locates that memory at 0x8100 0000. See the "Description"
section of Chapter 4 of the User Manual "External Memory Controller". The
reason should be clear if you read the third paragraph of the description and
make note of the 0x8100 0000 in the "Address Range" column of Table 27 which
immediately follows that paragraph.
The external memory controller (EMC) can support a wide range of timings. You
failed to provide critical information like the clock speed, but, I have no
doubt that it's possible to configure the EMC to accommodate a 55ns device. You
are going to have to spend some time with both the datasheet for the SRAM device
and the Bank Configuration Registers in Section 5 of Chapter 4 of the User
Manual in order to get the configuration set up correctly.
Norman
________________________________
From: zied130187
To: l...
Sent: Fri, May 20, 2011 11:07:15 AM
Subject: [lpc2000] Re: external SRAM with LPC2294
--- In l..., "zied130187" wrote:
>
> hello,
>
> i want to use an external SRAM (size 1M) with LPC2294 ?
>
> it have a problem if i use SRAM 8bit ?
>
> if i choose SRAM with access time 55ns , it have any problem ?
>
> thank you
>
any idea please ?
why the address of SRAM 1M in olimex LPC2294 is 0x81000000 ?
I can't, of course, speak for anyone other than myself, but, I do have a bit of
a feel for the nature of this group. Most likely nobody has responded for a
couple of reasons. First, this tends to be more of a software-oriented group
and you were asking a hardware design oriented question. The second reason,
however, is probably the more important reason since I know there are any number
of people out there who could answer your questions. Simply put, they are,
quite reasonably, not inclined to do more work on your problem than you appear
to have done yourself. To avoid that perception, you should start by visiting
the NXP site and read the relevant sections of the Datasheet and User Manual.
From the Datasheet: (Rev. 7)
6.7 External memory controller
The external Static Memory Controller is a module which provides an interface
between
the system bus and external (off-chip) memory devices. It provides support for
up to four
independently configurable memory banks (16 MB each with byte lane enable
control)
simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
EPROM,
burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
I haven't looked at the Olimex board, but, presumably it is accessing the
SRAM with CS1 which locates that memory at 0x8100 0000. See the "Description"
section of Chapter 4 of the User Manual "External Memory Controller". The
reason should be clear if you read the third paragraph of the description and
make note of the 0x8100 0000 in the "Address Range" column of Table 27 which
immediately follows that paragraph.
The external memory controller (EMC) can support a wide range of timings. You
failed to provide critical information like the clock speed, but, I have no
doubt that it's possible to configure the EMC to accommodate a 55ns device. You
are going to have to spend some time with both the datasheet for the SRAM device
and the Bank Configuration Registers in Section 5 of Chapter 4 of the User
Manual in order to get the configuration set up correctly.
Norman
________________________________
From: zied130187
To: l...
Sent: Fri, May 20, 2011 11:07:15 AM
Subject: [lpc2000] Re: external SRAM with LPC2294
--- In l..., "zied130187" wrote:
>
> hello,
>
> i want to use an external SRAM (size 1M) with LPC2294 ?
>
> it have a problem if i use SRAM 8bit ?
>
> if i choose SRAM with access time 55ns , it have any problem ?
>
> thank you
>
any idea please ?
why the address of SRAM 1M in olimex LPC2294 is 0x81000000 ?
Reply by ●May 20, 20112011-05-20
--- In l..., Norman Felder wrote:
>
> Hi,
>
> I can't, of course, speak for anyone other than myself, but, I do have a bit of
> a feel for the nature of this group. Most likely nobody has responded for a
> couple of reasons. First, this tends to be more of a software-oriented group
> and you were asking a hardware design oriented question. The second reason,
> however, is probably the more important reason since I know there are any number
> of people out there who could answer your questions. Simply put, they are,
> quite reasonably, not inclined to do more work on your problem than you appear
> to have done yourself. To avoid that perception, you should start by visiting
> the NXP site and read the relevant sections of the Datasheet and User Manual.
>
> From the Datasheet: (Rev. 7)
>
> 6.7 External memory controller
> The external Static Memory Controller is a module which provides an interface
> between
> the system bus and external (off-chip) memory devices. It provides support for
> up to four
> independently configurable memory banks (16 MB each with byte lane enable
> control)
> simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
> EPROM,
> burst ROM memory, or some external I/O devices.
> Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
>
> I haven't looked at the Olimex board, but, presumably it is accessing the
> SRAM with CS1 which locates that memory at 0x8100 0000. See the "Description"
> section of Chapter 4 of the User Manual "External Memory Controller". The
> reason should be clear if you read the third paragraph of the description and
> make note of the 0x8100 0000 in the "Address Range" column of Table 27 which
> immediately follows that paragraph.
>
> The external memory controller (EMC) can support a wide range of timings. You
> failed to provide critical information like the clock speed, but, I have no
> doubt that it's possible to configure the EMC to accommodate a 55ns device. You
> are going to have to spend some time with both the datasheet for the SRAM device
> and the Bank Configuration Registers in Section 5 of Chapter 4 of the User
> Manual in order to get the configuration set up correctly.
>
> Norman
>
Or maybe the sample code from Olimex. It wasn't hard to find where it set up the memory controller for external flash and external SRAM. I couldn't find any code that actually USED the SRAM but that's really a software issue (memory sections, linker script, etc).
A brief read of the promotional page shows the SRAM is rated for 12 nS access. It would still be worth looking at the datasheet.
Richard
Richard
>
> Hi,
>
> I can't, of course, speak for anyone other than myself, but, I do have a bit of
> a feel for the nature of this group. Most likely nobody has responded for a
> couple of reasons. First, this tends to be more of a software-oriented group
> and you were asking a hardware design oriented question. The second reason,
> however, is probably the more important reason since I know there are any number
> of people out there who could answer your questions. Simply put, they are,
> quite reasonably, not inclined to do more work on your problem than you appear
> to have done yourself. To avoid that perception, you should start by visiting
> the NXP site and read the relevant sections of the Datasheet and User Manual.
>
> From the Datasheet: (Rev. 7)
>
> 6.7 External memory controller
> The external Static Memory Controller is a module which provides an interface
> between
> the system bus and external (off-chip) memory devices. It provides support for
> up to four
> independently configurable memory banks (16 MB each with byte lane enable
> control)
> simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
> EPROM,
> burst ROM memory, or some external I/O devices.
> Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
>
> I haven't looked at the Olimex board, but, presumably it is accessing the
> SRAM with CS1 which locates that memory at 0x8100 0000. See the "Description"
> section of Chapter 4 of the User Manual "External Memory Controller". The
> reason should be clear if you read the third paragraph of the description and
> make note of the 0x8100 0000 in the "Address Range" column of Table 27 which
> immediately follows that paragraph.
>
> The external memory controller (EMC) can support a wide range of timings. You
> failed to provide critical information like the clock speed, but, I have no
> doubt that it's possible to configure the EMC to accommodate a 55ns device. You
> are going to have to spend some time with both the datasheet for the SRAM device
> and the Bank Configuration Registers in Section 5 of Chapter 4 of the User
> Manual in order to get the configuration set up correctly.
>
> Norman
>
Or maybe the sample code from Olimex. It wasn't hard to find where it set up the memory controller for external flash and external SRAM. I couldn't find any code that actually USED the SRAM but that's really a software issue (memory sections, linker script, etc).
A brief read of the promotional page shows the SRAM is rated for 12 nS access. It would still be worth looking at the datasheet.
Richard
Richard
Reply by ●May 23, 20112011-05-23
