Hay Guys,
I have been trying for over 2 weeks to get a definitive answer from NXP
technical support regarding this question...
When CPR1 is set is it possible for the processor to use the boot loader to save
data to the flash memory? That is, when my code needs to save operational
parameters to the processors flash memory can this be done by the processor
itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in
application programming, but also need to have my code protected from prying
eyes.
Regards,
MLC
LPC2148 CPR1 and IAP
Started by ●June 27, 2011
Reply by ●June 27, 20112011-06-27
--- In l..., "mlcchemtrac" wrote:
>
> Hay Guys,
>
> I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
>
> When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
>
> Regards,
> MLC
>
Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
If you need sample code for the LPC2148, see www.jcwren.com/arm
Richard
>
> Hay Guys,
>
> I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
>
> When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
>
> Regards,
> MLC
>
Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
If you need sample code for the LPC2148, see www.jcwren.com/arm
Richard
Reply by ●June 27, 20112011-06-27
--- In l..., "rtstofer" wrote:
>
>
>
> --- In l..., "mlcchemtrac" wrote:
> >
> > Hay Guys,
> >
> > I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
> >
> > When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
> >
> > Regards,
> > MLC
> >
>
> Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
>
> As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
>
> The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
>
> If you need sample code for the LPC2148, see www.jcwren.com/arm
>
> Richard
>
I'm looking in the LPC2387 manual here: http://www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf
this seems relevant (page 611, under CRP1):
Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
Write to RAM command can not access RAM below 0x40000200
Copy RAM to flash command can not write to Sector 0
Erase command can erase Sector 0 only when all sectors are
selected for erase
Compare command is disabled
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. Since compare command is
disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
so i believe the short answer is yes, anywhere except sector 0
>
>
>
> --- In l..., "mlcchemtrac" wrote:
> >
> > Hay Guys,
> >
> > I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
> >
> > When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
> >
> > Regards,
> > MLC
> >
>
> Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
>
> As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
>
> The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
>
> If you need sample code for the LPC2148, see www.jcwren.com/arm
>
> Richard
>
I'm looking in the LPC2387 manual here: http://www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf
this seems relevant (page 611, under CRP1):
Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
Write to RAM command can not access RAM below 0x40000200
Copy RAM to flash command can not write to Sector 0
Erase command can erase Sector 0 only when all sectors are
selected for erase
Compare command is disabled
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. Since compare command is
disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
so i believe the short answer is yes, anywhere except sector 0
Reply by ●June 27, 20112011-06-27
--- In l..., "christophe_faucon" wrote:
>
>
> --- In l..., "rtstofer" wrote:
> >
> >
> >
> > --- In l..., "mlcchemtrac" wrote:
> > >
> > > Hay Guys,
> > >
> > > I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
> > >
> > > When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
> > >
> > > Regards,
> > > MLC
> > >
> >
> > Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
> >
> > As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
> >
> > The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
> >
> > If you need sample code for the LPC2148, see www.jcwren.com/arm
> >
> > Richard
> >
>
> I'm looking in the LPC2387 manual here: http://www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf
>
> this seems relevant (page 611, under CRP1):
>
> Access to chip via the JTAG pins is disabled. This mode allows partial
> flash update using the following ISP commands and restrictions:
> Write to RAM command can not access RAM below 0x40000200
> Copy RAM to flash command can not write to Sector 0
> Erase command can erase Sector 0 only when all sectors are
> selected for erase
> Compare command is disabled
> This mode is useful when CRP is required and flash field updates are
> needed but all sectors can not be erased. Since compare command is
> disabled in case of partial updates the secondary loader should
> implement checksum mechanism to verify the integrity of the flash.
>
>
> so i believe the short answer is yes, anywhere except sector 0
>
For the lpc2148 (which the OP asked about), the restrictions are much more severe:
[QUOTE]
Code read protection is enabled by programming the flash address location 0x1FC (User flash sector 0) with value 0x8765 4321 (2271560481 Decimal). Address 0x1FC is used to
allow some room for the FIQ exception handler. When the code read protection is enabled the JTAG debug port, external memory boot and the following ISP commands are disabled:
Read Memory
Write to RAM
Go
Copy RAM to Flash
The ISP commands mentioned above terminate with return code CODE_READ_PROTECTION_ENABLED. The ISP erase command only allows erasure of all user sectors when the code read protection is enabled. This limitation does not exist if the code read protection is not enabled.
IAP commands are not affected by the code read protection. <------!
Important: CRP is active/inactive once the device has gone through a power cycle.
[/QUOTE]
Note where the UM specifically states that IAP commands are not affected by the code read protection. I skipped over that earlier.
IAP should work fine.
Richard
>
>
> --- In l..., "rtstofer" wrote:
> >
> >
> >
> > --- In l..., "mlcchemtrac" wrote:
> > >
> > > Hay Guys,
> > >
> > > I have been trying for over 2 weeks to get a definitive answer from NXP technical support regarding this question...
> > >
> > > When CPR1 is set is it possible for the processor to use the boot loader to save data to the flash memory? That is, when my code needs to save operational parameters to the processors flash memory can this be done by the processor itself, (IAP), if the CPR1 bit is set? I need to be able to do this, in application programming, but also need to have my code protected from prying eyes.
> > >
> > > Regards,
> > > MLC
> > >
> >
> > Why ask? It's a simple 5 minute exercise to just try it. Assuming you already have IAP working...
> >
> > As a GUESS, it's going to work fine. CRP is designed to keep JTAG dongles from reading program memory (plus a few other things).
> >
> > The User Manual is pretty clear that CRP disables JTAG debug and some ISP commands but it says not one word about CRP affecting IAP. The external bad guy has no access to IAP so there is no reason for CRP to get involved.
> >
> > If you need sample code for the LPC2148, see www.jcwren.com/arm
> >
> > Richard
> >
>
> I'm looking in the LPC2387 manual here: http://www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf
>
> this seems relevant (page 611, under CRP1):
>
> Access to chip via the JTAG pins is disabled. This mode allows partial
> flash update using the following ISP commands and restrictions:
> Write to RAM command can not access RAM below 0x40000200
> Copy RAM to flash command can not write to Sector 0
> Erase command can erase Sector 0 only when all sectors are
> selected for erase
> Compare command is disabled
> This mode is useful when CRP is required and flash field updates are
> needed but all sectors can not be erased. Since compare command is
> disabled in case of partial updates the secondary loader should
> implement checksum mechanism to verify the integrity of the flash.
>
>
> so i believe the short answer is yes, anywhere except sector 0
>
For the lpc2148 (which the OP asked about), the restrictions are much more severe:
[QUOTE]
Code read protection is enabled by programming the flash address location 0x1FC (User flash sector 0) with value 0x8765 4321 (2271560481 Decimal). Address 0x1FC is used to
allow some room for the FIQ exception handler. When the code read protection is enabled the JTAG debug port, external memory boot and the following ISP commands are disabled:
Read Memory
Write to RAM
Go
Copy RAM to Flash
The ISP commands mentioned above terminate with return code CODE_READ_PROTECTION_ENABLED. The ISP erase command only allows erasure of all user sectors when the code read protection is enabled. This limitation does not exist if the code read protection is not enabled.
IAP commands are not affected by the code read protection. <------!
Important: CRP is active/inactive once the device has gone through a power cycle.
[/QUOTE]
Note where the UM specifically states that IAP commands are not affected by the code read protection. I skipped over that earlier.
IAP should work fine.
Richard
