Hi

I', m trying to understand the difference of the two types of interrupts, system exceptions and peripheral interrupts.

I'm using uvision, in the header file the interrupts are defined as shown http://www.keil.com/dd/docs/arm/philips/lpc17xx.h

A sample of the defines is the following
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

/****** LPC17xx Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */
The user manual says that there are 35 vectored interrupts with 32 priority levels for each one.

I have already used the peripheral interrupts like this

__irq void TIMER0_IRQHandler(void) {
/* write code here */
/* list of all available flags, select which to use */
LPC_TIM0->IR = 1; /* Clear MAT0.0 interrupt flag */
LPC_TIM0->IR = 2; /* Clear MAT0.1 interrupt flag */
LPC_TIM0->IR = 4; /* Clear MAT0.2 interrupt flag */
LPC_TIM0->IR = 8; /* Clear MAT0.3 interrupt flag */
LPC_TIM0->IR = 16; /* Clear CAP0.0 interrupt flag */
LPC_TIM0->IR = 32; /* Clear CAP0.1 interrupt flag */
}

NVIC_EnableIRQ(TIMER0_IRQn); /* Enable TIMER0 interrupt */
NVIC_SetPriority(TIMER0_IRQn,0); /* Default priority group 0, can be 0(highest) - 31(lowest) */
my question is what is different with the processor exceptions, for example I have written the following and works fine

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

I'm not sure if the Processor Exceptions use a vectored interrupt and if there is an actual priority that can be programmed.
Why are these exceptions separated from the peripheral interrupts?
Can I use more that 35 interrupts (there are 35 vectors but the total available interrupts + exceptions are 41)?
I wasn't able to find any tutorial that explains this.

Thank you
Alex

Start a New Thread

There are a number of differences between processor exceptions and
interrupts.

They both behave in a similar manner so far as pushing state on entry but
the processor state is changed by processor exceptions, often setting
additional flags in the processor to indicate the fault status.

Many of the processor exceptions are non-recoverable, and also the return
address pushed depends on the type of exception occurring.

The LPC manual is not the correct place for this information, the best
reference is the AMMv7-M architecture reference manual which goes into great
detail about all the different exception types, their impact on the
processor state etc.

This is available from the ARM website, you just need to register before you
can download it.

Section B1.5

Regards

Phil.

From: l... [mailto:l...] On Behalf Of
a...@freemail.gr
Sent: 03 August 2011 18:49
To: l...
Subject: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

Hi

I', m trying to understand the difference of the two types of interrupts,
system exceptions and peripheral interrupts.

I'm using uvision, in the header file the interrupts are defined as shown
http://www.keil.com/dd/docs/arm/philips/lpc17xx.h

A sample of the defines is the following
/****** Cortex-M3 Processor Exceptions Numbers
***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

/****** LPC17xx Specific Interrupt Numbers
*******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */

The user manual says that there are 35 vectored interrupts with 32 priority
levels for each one.

I have already used the peripheral interrupts like this

__irq void TIMER0_IRQHandler(void) {
/* write code here */

/* list of all available flags, select which to use */
LPC_TIM0->IR = 1; /* Clear MAT0.0 interrupt flag */
LPC_TIM0->IR = 2; /* Clear MAT0.1 interrupt flag */
LPC_TIM0->IR = 4; /* Clear MAT0.2 interrupt flag */
LPC_TIM0->IR = 8; /* Clear MAT0.3 interrupt flag */
LPC_TIM0->IR = 16; /* Clear CAP0.0 interrupt flag */
LPC_TIM0->IR = 32; /* Clear CAP0.1 interrupt flag */
}

NVIC_EnableIRQ(TIMER0_IRQn); /* Enable TIMER0 interrupt */
NVIC_SetPriority(TIMER0_IRQn,0); /* Default priority group 0, can be
0(highest) - 31(lowest) */

my question is what is different with the processor exceptions, for example
I have written the following and works fine

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

I'm not sure if the Processor Exceptions use a vectored interrupt and if
there is an actual priority that can be programmed.
Why are these exceptions separated from the peripheral interrupts?
Can I use more that 35 interrupts (there are 35 vectors but the total
available interrupts + exceptions are 41)?
I wasn't able to find any tutorial that explains this.

Thank you
Alex Start a New Thread

Thank you for your answer,

my intension is basically to understand how to use these exception interrupts in the code, can you please tell me if declaring them the same way as the vectored inrterrupt is correct, like

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);
Alex
----- Original Message -----
From: Phil Young
To: l...
Sent: Wednesday, August 03, 2011 9:43 PM
Subject: RE: [lpc2000] LPC17xx difference between system exceptions and peripheral interrupts

There are a number of differences between processor exceptions and interrupts.

They both behave in a similar manner so far as pushing state on entry but the processor state is changed by processor exceptions, often setting additional flags in the processor to indicate the fault status.

Many of the processor exceptions are non-recoverable, and also the return address pushed depends on the type of exception occurring.

The LPC manual is not the correct place for this information, the best reference is the AMMv7-M architecture reference manual which goes into great detail about all the different exception types, their impact on the processor state etc.

This is available from the ARM website, you just need to register before you can download it.

Section B1.5

Regards

Phil.

From: l... [mailto:l...] On Behalf Of a...@freemail.gr
Sent: 03 August 2011 18:49
To: l...
Subject: [lpc2000] LPC17xx difference between system exceptions and peripheral interrupts

Hi

I', m trying to understand the difference of the two types of interrupts, system exceptions and peripheral interrupts.

I'm using uvision, in the header file the interrupts are defined as shown http://www.keil.com/dd/docs/arm/philips/lpc17xx.h

A sample of the defines is the following
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

/****** LPC17xx Specific Interrupt Numbers *************************************** ****************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */

The user manual says that there are 35 vectored interrupts with 32 priority levels for each one.

I have already used the peripheral interrupts like this

__irq void TIMER0_IRQHandler(void) {
/* write code here */

/* list of all available flags, select which to use */
LPC_TIM0->IR = 1; /* Clear MAT0.0 interrupt flag */
LPC_TIM0->IR = 2; /* Clear MAT0.1 interrupt flag */
LPC_TIM0->IR = 4; /* Clear MAT0.2 interrupt flag */
LPC_TIM0->IR = 8; /* Clear MAT0.3 interrupt flag */
LPC_TIM0->IR = 16; /* Clear CAP0.0 interrupt flag */
LPC_TIM0->IR = 32; /* Clear CAP0.1 interrupt flag */
}

NVIC_EnableIRQ(TIMER0_IRQn); /* Enable TIMER0 interrupt */
NVIC_SetPriority(TIMER0_IRQn,0); /* Default priority group 0, can be 0(highest) - 31(lowest) */

my question is what is different with the processor exceptions, for example I have written the following and works fine

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

I'm not sure if the Processor Exceptions use a vectored interrupt and if there is an actual priority that can be programmed.
Why are these exceptions separated from the peripheral interrupts?
Can I use more that 35 interrupts (there are 35 vectors but the total available interrupts + exceptions are 41)?
I wasn't able to find any tutorial that explains this.

Thank you
Alex Start a New Thread

Hi Alexan,

For the M3 it is not necessary to use the __irq prefix for an ISR handler,
simply declare a void function, the cortex takes care of pushing and
restoring all the registers anyway.

Processor exceptions use vectored interrupts, just like all other
exceptions, the vectors for all interrupts are fixed by HW since the
processor exceptions are hardwired in the core, and the peripheral
interrupts are fixed by assignment to the interrupt connections to the
interrupt controller.

Be cautious about setting the priorities, I haven't tried the prioritization
on the LPC17xx as I run just 2 handlers there, but on the LPC1114 I found
that the CMSIS code supplied with the original toolchain was incorrectly
computing the priority value.

Actually, according to the Keil manual __irq should generate a hard fault
since it forces the code to be generated as ARM code, but the cortex does
not support ARM mode and any attempt to execute in ARM mode should generate
a hard fault.

Regards

Phil.

From: l... [mailto:l...] On Behalf Of
Alexan_e
Sent: 03 August 2011 21:25
To: l...
Subject: Re: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

Thank you for your answer,

my intension is basically to understand how to use these exception
interrupts in the code, can you please tell me if declaring them the same
way as the vectored inrterrupt is correct, like

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

Alex

----- Original Message -----

From: Phil Young

To: l...

Sent: Wednesday, August 03, 2011 9:43 PM

Subject: RE: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

There are a number of differences between processor exceptions and
interrupts.

They both behave in a similar manner so far as pushing state on entry but
the processor state is changed by processor exceptions, often setting
additional flags in the processor to indicate the fault status.

Many of the processor exceptions are non-recoverable, and also the return
address pushed depends on the type of exception occurring.

The LPC manual is not the correct place for this information, the best
reference is the AMMv7-M architecture reference manual which goes into great
detail about all the different exception types, their impact on the
processor state etc.

This is available from the ARM website, you just need to register before you
can download it.

Section B1.5

Regards

Phil.

From: l... [mailto:l...] On Behalf Of
a...@freemail.gr
Sent: 03 August 2011 18:49
To: l...
Subject: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

Hi

I', m trying to understand the difference of the two types of interrupts,
system exceptions and peripheral interrupts.

I'm using uvision, in the header file the interrupts are defined as shown
http://www.keil.com/dd/docs/arm/philips/lpc17xx.h

A sample of the defines is the following
/****** Cortex-M3 Processor Exceptions Numbers
***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

/****** LPC17xx Specific Interrupt Numbers
*************************************** ****************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */

The user manual says that there are 35 vectored interrupts with 32 priority
levels for each one.

I have already used the peripheral interrupts like this

__irq void TIMER0_IRQHandler(void) {
/* write code here */

/* list of all available flags, select which to use */
LPC_TIM0->IR = 1; /* Clear MAT0.0 interrupt flag */
LPC_TIM0->IR = 2; /* Clear MAT0.1 interrupt flag */
LPC_TIM0->IR = 4; /* Clear MAT0.2 interrupt flag */
LPC_TIM0->IR = 8; /* Clear MAT0.3 interrupt flag */
LPC_TIM0->IR = 16; /* Clear CAP0.0 interrupt flag */
LPC_TIM0->IR = 32; /* Clear CAP0.1 interrupt flag */
}

NVIC_EnableIRQ(TIMER0_IRQn); /* Enable TIMER0 interrupt */
NVIC_SetPriority(TIMER0_IRQn,0); /* Default priority group 0, can be
0(highest) - 31(lowest) */

my question is what is different with the processor exceptions, for example
I have written the following and works fine

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

I'm not sure if the Processor Exceptions use a vectored interrupt and if
there is an actual priority that can be programmed.
Why are these exceptions separated from the peripheral interrupts?
Can I use more that 35 interrupts (there are 35 vectors but the total
available interrupts + exceptions are 41)?
I wasn't able to find any tutorial that explains this.

Thank you
Alex Start a New Thread

You are right of course about the __irq, thank you for pointing this.
I was just testing the code using the uvision simulator and it was working fine with __irq so I thought it was the correct way but now that you have mentioned it I have opened the included examples and there is no prefix anywhere (and works fine too)

Basically I was adding the LPC178x/7x to ARMwizard and I was going through the interrupts in the user manual of NXP and I couldn't find the SysTick interrupt in the interrupt table (NVIC section) but I was sure there was one because it was mentioned in the system tick timer section.
Anyway I checked the header file in uvision and then I noticed that there was a group of exception interrupts that I hadn't included for any of the 175x/6x either.
I had no idea how they should be used or if I should include these along with the peripheral interrupts but since they are used the same way I guess I should add them in the list with the other available interrupts.

Alex

----- Original Message -----
From: Phil Young
To: l...
Sent: Thursday, August 04, 2011 1:19 AM
Subject: RE: [lpc2000] LPC17xx difference between system exceptions and peripheral interrupts

Hi Alexan,

For the M3 it is not necessary to use the __irq prefix for an ISR handler, simply declare a void function, the cortex takes care of pushing and restoring all the registers anyway.

Processor exceptions use vectored interrupts, just like all other exceptions, the vectors for all interrupts are fixed by HW since the processor exceptions are hardwired in the core, and the peripheral interrupts are fixed by assignment to the interrupt connections to the interrupt controller.

Be cautious about setting the priorities, I haven't tried the prioritization on the LPC17xx as I run just 2 handlers there, but on the LPC1114 I found that the CMSIS code supplied with the original toolchain was incorrectly computing the priority value.

Actually, according to the Keil manual __irq should generate a hard fault since it forces the code to be generated as ARM code, but the cortex does not support ARM mode and any attempt to execute in ARM mode should generate a hard fault.

Regards

Phil.

From: l... [mailto:l...] On Behalf Of Alexan_e
Sent: 03 August 2011 21:25
To: l...
Subject: Re: [lpc2000] LPC17xx difference between system exceptions and peripheral interrupts

Thank you for your answer,

my intension is basically to understand how to use these exception interrupts in the code, can you please tell me if declaring them the same way as the vectored inrterrupt is correct, like

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

Alex Start a New Thread

Hi Alex

Actually you don't need to define anything for the interrupts you don't
handle.

The default behaviour of them is defined in startup.s using weak references,
so if you define them just define a function with the same name and it will
override the weak reference when it is linked, otherwise they default to
just loops.

Regards

Phil.

From: l... [mailto:l...] On Behalf Of
Alexan_e
Sent: 03 August 2011 23:58
To: l...
Subject: Re: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

You are right of course about the __irq, thank you for pointing this.

I was just testing the code using the uvision simulator and it was working
fine with __irq so I thought it was the correct way but now that you have
mentioned it I have opened the included examples and there is no prefix
anywhere (and works fine too)

Basically I was adding the LPC178x/7x to ARMwizard and I was going through
the interrupts in the user manual of NXP and I couldn't find the SysTick
interrupt in the interrupt table (NVIC section) but I was sure there was one
because it was mentioned in the system tick timer section.

Anyway I checked the header file in uvision and then I noticed that there
was a group of exception interrupts that I hadn't included for any of the
175x/6x either.

I had no idea how they should be used or if I should include these along
with the peripheral interrupts but since they are used the same way I guess
I should add them in the list with the other available interrupts.

Alex

----- Original Message -----

From: Phil Young

To: l...

Sent: Thursday, August 04, 2011 1:19 AM

Subject: RE: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

Hi Alexan,

For the M3 it is not necessary to use the __irq prefix for an ISR handler,
simply declare a void function, the cortex takes care of pushing and
restoring all the registers anyway.

Processor exceptions use vectored interrupts, just like all other
exceptions, the vectors for all interrupts are fixed by HW since the
processor exceptions are hardwired in the core, and the peripheral
interrupts are fixed by assignment to the interrupt connections to the
interrupt controller.

Be cautious about setting the priorities, I haven't tried the prioritization
on the LPC17xx as I run just 2 handlers there, but on the LPC1114 I found
that the CMSIS code supplied with the original toolchain was incorrectly
computing the priority value.

Actually, according to the Keil manual __irq should generate a hard fault
since it forces the code to be generated as ARM code, but the cortex does
not support ARM mode and any attempt to execute in ARM mode should generate
a hard fault.

Regards

Phil.

From: l... [mailto:l...] On Behalf Of
Alexan_e
Sent: 03 August 2011 21:25
To: l...
Subject: Re: [lpc2000] LPC17xx difference between system exceptions and
peripheral interrupts

Thank you for your answer,

my intension is basically to understand how to use these exception
interrupts in the code, can you please tell me if declaring them the same
way as the vectored inrterrupt is correct, like

__irq void SysTick_Handler(void) {
/* write code here */

}

NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn,0);

Alex Start a New Thread

In ARMwizard ( http://alexan.edaboard.eu/index.php?page=armwizard ) I have a dropdown list and the user can select any of the available interrupts and then the initialization code and interrupt functions are generated automatically.
I meant that the exception interrupts were not listed there and I should add them along with the rest of the peripheral interrupts.

Thank you again for all you help
Alex

On 08/04/2011 03:27 AM, Phil Young wrote:

> Hi Alex
>
> Actually you don't need to define anything for the interrupts you don't
> handle.
>
> The default behaviour of them is defined in startup.s using weak references,
> so if you define them just define a function with the same name and it will
> override the weak reference when it is linked, otherwise they default to
> just loops.
>
> Regards
>
> Phil.
Start a New Thread