Hi Everybody,

what I am trying to do is:
1) fill fifo at slave side using CPU
2) init GPDMA for SSP slave transfer
3) wait for master to start transfer
5) when transfers from master and slave are finished I block at slave side
GPDMA channels and reload fifo (using CPU) and wait for master to send next
package.

This way I expect to have valid data at master side- because I fill the
fifo, so when master clock appears I got valid data. The problem is that
this fifo filling works only once, at first transfer- I can see in master
buffer that I have correct data. After every next transfer I got rubbish in
first 8 words (fifo size) in the master's buffer (but data beyond 8th word
are correct). I checked the SSP status register and it says that TX fifo is
full- even when I got slave GPDMA interrupt: TX transfer end. So I am not
able to push new data into fifo. After every slave transfer I'm switching
off GPDMA requests in the SSPxDMACR register and block GPDMA channels. It
seems to me that if I turn on once GPDMA support for the SSP, I can't go
back to software support (using CPU). Do you Guys know what I am missing
here?
Regards,
Kuba


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Hi Kuba,

I have SSP+GPDMA working on an LPC1769. All you need are 2 DMA channels
on respectively transmit and receive: transmit to load the data and
receive to monitor the bus activity (it will inform you when the FIFO is
empty).

There are sample projects on the web for the LPC176x with LPCXpresso
that can get you going.

Cheers
Olivier

Kuba Dorzak wrote:
>
> Hi Everybody,
>
> what I am trying to do is:
> 1) fill fifo at slave side using CPU
> 2) init GPDMA for SSP slave transfer
> 3) wait for master to start transfer
> 5) when transfers from master and slave are finished I block at slave side
> GPDMA channels and reload fifo (using CPU) and wait for master to send
> next
> package.
>
> This way I expect to have valid data at master side- because I fill the
> fifo, so when master clock appears I got valid data. The problem is that
> this fifo filling works only once, at first transfer- I can see in master
> buffer that I have correct data. After every next transfer I got
> rubbish in
> first 8 words (fifo size) in the master's buffer (but data beyond 8th word
> are correct). I checked the SSP status register and it says that TX
> fifo is
> full- even when I got slave GPDMA interrupt: TX transfer end. So I am not
> able to push new data into fifo. After every slave transfer I'm switching
> off GPDMA requests in the SSPxDMACR register and block GPDMA channels. It
> seems to me that if I turn on once GPDMA support for the SSP, I can't go
> back to software support (using CPU). Do you Guys know what I am missing
> here?
>
> Regards,
> Kuba
>
>
--

Olivier Gautherot
*Email:* o...@gautherot.net
*Cel:* +56 98 730 9361
*Web:* www.gautherot.net
*LinkedIn:* http://www.linkedin.com/in/ogautherot



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