The LPC11Axx PLL is designed to multiplies the input frequency, NOT DIVIDING IT.
You cannot convert core speed 12Mhz to 50kHz. Use the divider in your peripheral
or use slower crystal as the main frequency.
Regards,
-daniel
Power Down LPC11A14
Started by ●May 8, 2013
Reply by ●May 10, 20132013-05-10
Reply by ●May 10, 20132013-05-10
Reply by ●May 10, 20132013-05-10
Which part of User Manual ?
The PLL only operates in single mode: Fclkout = M x Fclkin (M=1..32). So there's no way the PLL output will be less than input clock.
Regards,
-daniel
The PLL only operates in single mode: Fclkout = M x Fclkin (M=1..32). So there's no way the PLL output will be less than input clock.
Regards,
-daniel
Reply by ●May 10, 20132013-05-10
I see your point, but take a look at page 284 where they show an example of
creating a 40kHz clock, and explain why it is not possible. But using their
example would indicate that 50kHz should be possible. It looks like there
is a system clock divider after the PLL that would allow this.
Mike
creating a 40kHz clock, and explain why it is not possible. But using their
example would indicate that 50kHz should be possible. It looks like there
is a system clock divider after the PLL that would allow this.
Mike
Reply by ●May 10, 20132013-05-10
How about System clock divider register (SYSAHBCLKDIV) ? The UM says :
This register controls how the main clock is divided to provide the system
clock to the core, memories, and the peripherals. The system clock can be
shut down completely by setting the DIV field to zero. (Page 21)
I tried this register
LPC_SYSCON->SYSAHBCLKDIV = value; // 1...255
However there was no change in the power consumption. Does that mean we
have to update clock or something, because the UM does not say anything
like that and neither it is done in any example codes.
Rgds
Shashank
This register controls how the main clock is divided to provide the system
clock to the core, memories, and the peripherals. The system clock can be
shut down completely by setting the DIV field to zero. (Page 21)
I tried this register
LPC_SYSCON->SYSAHBCLKDIV = value; // 1...255
However there was no change in the power consumption. Does that mean we
have to update clock or something, because the UM does not say anything
like that and neither it is done in any example codes.
Rgds
Shashank
Reply by ●May 10, 20132013-05-10
@Michael... Yes thats what has been bothering me. According to that set_pll
must work. However the system hangs !
must work. However the system hangs !
Reply by ●May 10, 20132013-05-10
Il 10/05/2013 07:43, Shashank Maheshwari ha scritto:
> @Michael... Yes thats what has been bothering me. According to that set_pll
> must work. However the system hangs !
Technically there is no reason to use the PLL if you need a FCLK less
then the crystal or IRC frequency, it is better to power down the PLL.
Then, to change the post and feedback dividers of the PLL you have to
power down the PLL instead there is no guarantee that the PLL locks to
the new frequency. And remember that there is the low frequency
oscillator (LFOSC) that should be used instead the PLL to produce lower
frequencies.
> @Michael... Yes thats what has been bothering me. According to that set_pll
> must work. However the system hangs !
Technically there is no reason to use the PLL if you need a FCLK less
then the crystal or IRC frequency, it is better to power down the PLL.
Then, to change the post and feedback dividers of the PLL you have to
power down the PLL instead there is no guarantee that the PLL locks to
the new frequency. And remember that there is the low frequency
oscillator (LFOSC) that should be used instead the PLL to produce lower
frequencies.
Reply by ●May 10, 20132013-05-10
According to the convention, a low frequency should reduce the power
consumption. However when I use LF Oscillator at its lowest frequency and
shut down the IRC, IRC Output and PLL the current consumption does not seem
to change. The IC still consumes around 8-9mA.
What can be the other issues here ? Any other thing needs to be configured
to reduce power consumption while using the LFO?
On Fri, May 10, 2013 at 12:17 PM, M. Manca wrote:
consumption. However when I use LF Oscillator at its lowest frequency and
shut down the IRC, IRC Output and PLL the current consumption does not seem
to change. The IC still consumes around 8-9mA.
What can be the other issues here ? Any other thing needs to be configured
to reduce power consumption while using the LFO?
On Fri, May 10, 2013 at 12:17 PM, M. Manca wrote:
Reply by ●May 10, 20132013-05-10
Il 10/05/2013 09:10, Shashank Maheshwari ha scritto:
> According to the convention, a low frequency should reduce the power
> consumption. However when I use LF Oscillator at its lowest frequency and
> shut down the IRC, IRC Output and PLL the current consumption does not seem
> to change. The IC still consumes around 8-9mA.
There are many things that you aren't considering or you are doing wrong
because at 12MHz with PLL and SYSOSC disabled in power down you should
have a power consumption around 2 mA. Check also if internal pull up and
pull down resistors are disabled or not.
From your data I suppose that PLL isn't power down properly. The PLL
current consumption is about 2 - 2.5 mA so you should see clearly when
it is up or down.
If you don't need the EEPROM inside the LPC11Axx series you should check
the LPC11xxLV family that provides more power down modes and that could
reach about 1.6-2.0 uA current consumption in deep sleep mode.
> According to the convention, a low frequency should reduce the power
> consumption. However when I use LF Oscillator at its lowest frequency and
> shut down the IRC, IRC Output and PLL the current consumption does not seem
> to change. The IC still consumes around 8-9mA.
There are many things that you aren't considering or you are doing wrong
because at 12MHz with PLL and SYSOSC disabled in power down you should
have a power consumption around 2 mA. Check also if internal pull up and
pull down resistors are disabled or not.
From your data I suppose that PLL isn't power down properly. The PLL
current consumption is about 2 - 2.5 mA so you should see clearly when
it is up or down.
If you don't need the EEPROM inside the LPC11Axx series you should check
the LPC11xxLV family that provides more power down modes and that could
reach about 1.6-2.0 uA current consumption in deep sleep mode.
Reply by ●May 10, 20132013-05-10
Thanks for that input Manca. This group is a real saver! So I was just
trying out all the alternatives and following is the result :
Before going into sleep mode WFI(), I turn on the LF Oscillator at its
lowest frequency (600/64 = 9.575kHz). I turn down the IRC oscillator output
power, IRC power, ADC, XTAL, Watchdog, DAC and analog comparator. However I
have not turned down the Flash Power (I guess if I turn this down, this
will hang the system as how would the processor fetch code ?)
Now I get a sleep current of 1.48mA which is still pretty high. I have
turned all the GPIOs as outputs and driven low.
What else can I do?
Best Regards
Shashank
trying out all the alternatives and following is the result :
Before going into sleep mode WFI(), I turn on the LF Oscillator at its
lowest frequency (600/64 = 9.575kHz). I turn down the IRC oscillator output
power, IRC power, ADC, XTAL, Watchdog, DAC and analog comparator. However I
have not turned down the Flash Power (I guess if I turn this down, this
will hang the system as how would the processor fetch code ?)
Now I get a sleep current of 1.48mA which is still pretty high. I have
turned all the GPIOs as outputs and driven low.
What else can I do?
Best Regards
Shashank
