No official announcement yet (or i have overseen it...)
but they have posted at least a bit more new info about
the LPC4370:

http://www.nxp.com/products/microcontrollers/cortex_m4/LPC4370FET256.html

"The LPC4370 include an application ARM Cortex-M0 coprocessor and a
second ARM Cortex-M0 subsystem for managing the SGPIO and SPI
peripherals. The ARM Cortex-M0 core is an energy-efficient and
easy-to-use 32-bit core which is code- and tool-compatible with the
Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance
with a simple instruction set and reduced code size."

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I understood that it doesn't mean triple core. It is CM4 + CM0, where CM0
controls the SGPIO and SPI. Nice.
On Sat, Jul 20, 2013 at 5:29 PM, capiman26061973 wrote:

> **
> No official announcement yet (or i have overseen it...)
> but they have posted at least a bit more new info about
> the LPC4370:
>
> http://www.nxp.com/products/microcontrollers/cortex_m4/LPC4370FET256.html
>
> "The LPC4370 include an application ARM Cortex-M0 coprocessor and a
> second ARM Cortex-M0 subsystem for managing the SGPIO and SPI
> peripherals. The ARM Cortex-M0 core is an energy-efficient and
> easy-to-use 32-bit core which is code- and tool-compatible with the
> Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance
> with a simple instruction set and reduced code size."
>
>
>

--
Skype: felipeanl
[Non-text portions of this message have been removed]

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No no no. I was wrong. It is a triple core: 32-bit ARM Cortex-M4 + 2 x M0
MCU;

On Sat, Jul 20, 2013 at 6:21 PM, Felipe de Andrade Neves Lavratti <
f...@gmail.com> wrote:

> I understood that it doesn't mean triple core. It is CM4 + CM0, where CM0
> controls the SGPIO and SPI. Nice.
> On Sat, Jul 20, 2013 at 5:29 PM, capiman26061973 wrote:
>
>> **
>> No official announcement yet (or i have overseen it...)
>> but they have posted at least a bit more new info about
>> the LPC4370:
>>
>> http://www.nxp.com/products/microcontrollers/cortex_m4/LPC4370FET256.html
>>
>> "The LPC4370 include an application ARM Cortex-M0 coprocessor and a
>> second ARM Cortex-M0 subsystem for managing the SGPIO and SPI
>> peripherals. The ARM Cortex-M0 core is an energy-efficient and
>> easy-to-use 32-bit core which is code- and tool-compatible with the
>> Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance
>> with a simple instruction set and reduced code size."
>>
>>
>> --
> Skype: felipeanl
--
Skype: felipeanl
[Non-text portions of this message have been removed]

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On 20 Jul 2013, at 22:23, Felipe de Andrade Neves Lavratti wrote:

> No no no. I was wrong. It is a triple core: 32-bit ARM Cortex-M4 + 2 x M0
> MCU;
>

You can find it has three cores by looking at the JTAG chain

-- Paul.

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Hi

I have just checked the NXP site for the LPC4370 and all traces of it seemed to have been withdrawn. I am sure (?) it was listed under the LPC43xx series a few weeks ago.

Does this mean that there will be no M4/M0/M0 chip coming - I sure would have a use for it.

John.

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