SSP: How to clear transmit FIFO

Started by Gerhard Unrecht April 14, 2005
Hey,

I want to clear the transmit-Fifo, to have a defined state.
Knows anybody how to do do this?

Regards

Gerhard Unrecht


An Engineer's Guide to the LPC2100 Series


There are two ways to do this:
1. Disable the FIFO enable bit on the FIFO control register
2. Set the Tx FIFO reset bit ont the FIFO control register

Ken Wada

--- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...> wrote:
> Hey,
>
> I want to clear the transmit-Fifo, to have a defined state.
> Knows anybody how to do do this?
>
> Regards
>
> Gerhard Unrecht >




Beware the fine print that FIFO enable bit must be set for proper
operation of the UART! --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
>
> There are two ways to do this:
> 1. Disable the FIFO enable bit on the FIFO control register
> 2. Set the Tx FIFO reset bit ont the FIFO control register
>
> Ken Wada
>
> --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
wrote:
> > Hey,
> >
> > I want to clear the transmit-Fifo, to have a defined state.
> > Knows anybody how to do do this?
> >
> > Regards
> >
> > Gerhard Unrecht
> >
> >
> >




I noticed the comment on 'proper UART' operation also.

I have used both the 16c550 and the 16c450 for many years. My
recollection is that the FIFO enable bit was supposed to change the
mode to 16c450 'FIFO-less' operation when disabled; and change the
mode to true 16c550 mode when enabled.

In fact, the National Semiconductor datasheet on the 16c550 says the
following:

Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
changing from the FIFO Mode to the 16450 Mode and vice versa, data is
automatically cleared from the FIFOs. This bit must be a 1 when other
FCR bits are written to or they will not be programmed.

It was my understanding, according to the LPC2xxx user's manual, and
datasheet that, (other than not supporting the DMA operation), that
these UARTS are supposed to be 16c550 clones.

Ken Wada

--- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
>
> Beware the fine print that FIFO enable bit must be set for proper
> operation of the UART! > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> >
> > There are two ways to do this:
> > 1. Disable the FIFO enable bit on the FIFO control register
> > 2. Set the Tx FIFO reset bit ont the FIFO control register
> >
> > Ken Wada
> >
> > --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
> wrote:
> > > Hey,
> > >
> > > I want to clear the transmit-Fifo, to have a defined state.
> > > Knows anybody how to do do this?
> > >
> > > Regards
> > >
> > > Gerhard Unrecht
> > >
> > >
> > >




Thank you Ben,
I'm sorry, but it's about the SSP (SPI1) not the UART.
I found no CLR or ENABLE-Bit !
Regard
Gerhard Unrecht

--- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
>
> I noticed the comment on 'proper UART' operation also.
>
> I have used both the 16c550 and the 16c450 for many years. My
> recollection is that the FIFO enable bit was supposed to change
the
> mode to 16c450 'FIFO-less' operation when disabled; and change the
> mode to true 16c550 mode when enabled.
>
> In fact, the National Semiconductor datasheet on the 16c550 says
the
> following:
>
> Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
> changing from the FIFO Mode to the 16450 Mode and vice versa, data
is
> automatically cleared from the FIFOs. This bit must be a 1 when
other
> FCR bits are written to or they will not be programmed.
>
> It was my understanding, according to the LPC2xxx user's manual,
and
> datasheet that, (other than not supporting the DMA operation),
that
> these UARTS are supposed to be 16c550 clones.
>
> Ken Wada
>
> --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> >
> > Beware the fine print that FIFO enable bit must be set for
proper
> > operation of the UART!
> >
> >
> > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> > >
> > > There are two ways to do this:
> > > 1. Disable the FIFO enable bit on the FIFO control register
> > > 2. Set the Tx FIFO reset bit ont the FIFO control register
> > >
> > > Ken Wada
> > >
> > > --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
> > wrote:
> > > > Hey,
> > > >
> > > > I want to clear the transmit-Fifo, to have a defined state.
> > > > Knows anybody how to do do this?
> > > >
> > > > Regards
> > > >
> > > > Gerhard Unrecht
> > > >
> > > >
> > > >




My understanding is that this was Philips' original plan. However,
they they discovered a bug in the operation when the FIFO is
disabled, so they just added that note saying: Don't do it!
--- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
>
> I noticed the comment on 'proper UART' operation also.
>
> I have used both the 16c550 and the 16c450 for many years. My
> recollection is that the FIFO enable bit was supposed to change the
> mode to 16c450 'FIFO-less' operation when disabled; and change the
> mode to true 16c550 mode when enabled.
>
> In fact, the National Semiconductor datasheet on the 16c550 says
the
> following:
>
> Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
> changing from the FIFO Mode to the 16450 Mode and vice versa, data
is
> automatically cleared from the FIFOs. This bit must be a 1 when
other
> FCR bits are written to or they will not be programmed.
>
> It was my understanding, according to the LPC2xxx user's manual,
and
> datasheet that, (other than not supporting the DMA operation), that
> these UARTS are supposed to be 16c550 clones.
>
> Ken Wada
>
> --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> >
> > Beware the fine print that FIFO enable bit must be set for proper
> > operation of the UART!
> >
> >
> > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> > >
> > > There are two ways to do this:
> > > 1. Disable the FIFO enable bit on the FIFO control register
> > > 2. Set the Tx FIFO reset bit ont the FIFO control register
> > >
> > > Ken Wada
> > >
> > > --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
> > wrote:
> > > > Hey,
> > > >
> > > > I want to clear the transmit-Fifo, to have a defined state.
> > > > Knows anybody how to do do this?
> > > >
> > > > Regards
> > > >
> > > > Gerhard Unrecht
> > > >
> > > >
> > > >




say....
Have you tried this? If so, what happens? Does the UART lockup or
something like that?

It did not occur to me to try something like this.

I suppose something bad probably will happen.

Ken Wada

--- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
>
> My understanding is that this was Philips' original plan. However,
> they they discovered a bug in the operation when the FIFO is
> disabled, so they just added that note saying: Don't do it! >
> --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> >
> > I noticed the comment on 'proper UART' operation also.
> >
> > I have used both the 16c550 and the 16c450 for many years. My
> > recollection is that the FIFO enable bit was supposed to change
the
> > mode to 16c450 'FIFO-less' operation when disabled; and change the
> > mode to true 16c550 mode when enabled.
> >
> > In fact, the National Semiconductor datasheet on the 16c550 says
> the
> > following:
> >
> > Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> > FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
> > changing from the FIFO Mode to the 16450 Mode and vice versa, data
> is
> > automatically cleared from the FIFOs. This bit must be a 1 when
> other
> > FCR bits are written to or they will not be programmed.
> >
> > It was my understanding, according to the LPC2xxx user's manual,
> and
> > datasheet that, (other than not supporting the DMA operation),
that
> > these UARTS are supposed to be 16c550 clones.
> >
> > Ken Wada
> >
> > --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> > >
> > > Beware the fine print that FIFO enable bit must be set for
proper
> > > operation of the UART!
> > >
> > >
> > > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > There are two ways to do this:
> > > > 1. Disable the FIFO enable bit on the FIFO control register
> > > > 2. Set the Tx FIFO reset bit ont the FIFO control register
> > > >
> > > > Ken Wada
> > > >
> > > > --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
> > > wrote:
> > > > > Hey,
> > > > >
> > > > > I want to clear the transmit-Fifo, to have a defined state.
> > > > > Knows anybody how to do do this?
> > > > >
> > > > > Regards
> > > > >
> > > > > Gerhard Unrecht
> > > > >
> > > > >
> > > > >




The SPI does not have a FIFO.

The SPI device is basically a shift register. There really is no need
for an enable or clear on the SPI interface.

Ken Wada

--- In lpc2000@lpc2..., "gerhard_unrecht" <unrecht@p...>
wrote:
>
> Thank you Ben,
> I'm sorry, but it's about the SSP (SPI1) not the UART.
> I found no CLR or ENABLE-Bit !
> Regard
> Gerhard Unrecht
>
> --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> >
> > I noticed the comment on 'proper UART' operation also.
> >
> > I have used both the 16c550 and the 16c450 for many years. My
> > recollection is that the FIFO enable bit was supposed to change
> the
> > mode to 16c450 'FIFO-less' operation when disabled; and change the
> > mode to true 16c550 mode when enabled.
> >
> > In fact, the National Semiconductor datasheet on the 16c550 says
> the
> > following:
> >
> > Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> > FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
> > changing from the FIFO Mode to the 16450 Mode and vice versa, data
> is
> > automatically cleared from the FIFOs. This bit must be a 1 when
> other
> > FCR bits are written to or they will not be programmed.
> >
> > It was my understanding, according to the LPC2xxx user's manual,
> and
> > datasheet that, (other than not supporting the DMA operation),
> that
> > these UARTS are supposed to be 16c550 clones.
> >
> > Ken Wada
> >
> > --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> > >
> > > Beware the fine print that FIFO enable bit must be set for
> proper
> > > operation of the UART!
> > >
> > >
> > > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > There are two ways to do this:
> > > > 1. Disable the FIFO enable bit on the FIFO control register
> > > > 2. Set the Tx FIFO reset bit ont the FIFO control register
> > > >
> > > > Ken Wada
> > > >
> > > > --- In lpc2000@lpc2..., Gerhard Unrecht <unrecht@p...>
> > > wrote:
> > > > > Hey,
> > > > >
> > > > > I want to clear the transmit-Fifo, to have a defined state.
> > > > > Knows anybody how to do do this?
> > > > >
> > > > > Regards
> > > > >
> > > > > Gerhard Unrecht
> > > > >
> > > > >
> > > > >




I have not tried this. If the Data Book says don't do it - I
listen. I would rather not find out what problem it causes after
shipping 5000 units to customers. --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
>
> say....
> Have you tried this? If so, what happens? Does the UART lockup or
> something like that?
>
> It did not occur to me to try something like this.
>
> I suppose something bad probably will happen.
>
> Ken Wada
>
> --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> >
> > My understanding is that this was Philips' original plan.
However,
> > they they discovered a bug in the operation when the FIFO is
> > disabled, so they just added that note saying: Don't do it!
> >
> >
> >
> > --- In lpc2000@lpc2..., "Ken Wada" <kwada@a...> wrote:
> > >
> > > I noticed the comment on 'proper UART' operation also.
> > >
> > > I have used both the 16c550 and the 16c450 for many years. My
> > > recollection is that the FIFO enable bit was supposed to change
> the
> > > mode to 16c450 'FIFO-less' operation when disabled; and change
the
> > > mode to true 16c550 mode when enabled.
> > >
> > > In fact, the National Semiconductor datasheet on the 16c550
says
> > the
> > > following:
> > >
> > > Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> > > FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When
> > > changing from the FIFO Mode to the 16450 Mode and vice versa,
data
> > is
> > > automatically cleared from the FIFOs. This bit must be a 1 when
> > other
> > > FCR bits are written to or they will not be programmed.
> > >
> > > It was my understanding, according to the LPC2xxx user's
manual,
> > and
> > > datasheet that, (other than not supporting the DMA operation),
> that
> > > these UARTS are supposed to be 16c550 clones.
> > >
> > > Ken Wada
> > >
> > > --- In lpc2000@lpc2..., "lp2000c" <lp2000c@e...> wrote:
> > > >
> > > > Beware the fine print that FIFO enable bit must be set for
> proper
> > > > operation of the UART!