100 MHz clock using LPC2138
Started by ●June 12, 2005
Dear All,
I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the same. Match functionality is inappropriate for generating such high frequency.
Sudip
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Reply by ●June 12, 20052005-06-12
----- Original Message -----
From: "sudip nag" <sudipnag1@sudi...>
To: <lpc2000@lpc2...>
Sent: Sunday, June 12, 2005 7:16 AM
Subject: [lpc2000] 100 MHz clock using LPC2138 >
>
> Dear All,
>
> I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1
> MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the
> same. Match functionality is inappropriate for generating such high
> frequency.
A PLL sythesiser is the best way, with a programmable divider controlled by
the '2138. You could use a synthesiser chip like those from Nat. Semi. and a
VCO, or make your own synthesiser.
Leon
--
Leon Heller, G1HSM
leon.heller@leon...
http://webspace.webring.com/people/jl/leon_heller/
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From: "sudip nag" <sudipnag1@sudi...>
To: <lpc2000@lpc2...>
Sent: Sunday, June 12, 2005 7:16 AM
Subject: [lpc2000] 100 MHz clock using LPC2138 >
>
> Dear All,
>
> I would like to generate 60 MHz to 100 MHz clock, in controlled step of 1
> MHz, with 50% duty cycle using LPC2138. Any suggestion how to generate the
> same. Match functionality is inappropriate for generating such high
> frequency.
A PLL sythesiser is the best way, with a programmable divider controlled by
the '2138. You could use a synthesiser chip like those from Nat. Semi. and a
VCO, or make your own synthesiser.
Leon
--
Leon Heller, G1HSM
leon.heller@leon...
http://webspace.webring.com/people/jl/leon_heller/
---
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to maintain up to date anti virus software on the device that you are
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Reply by ●June 12, 20052005-06-12
--- In lpc2000@lpc2..., sudip nag <sudipnag1@y...> wrote:
> I would like to generate 60 MHz to 100 MHz clock, in controlled step
of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
generate the same. Match functionality is inappropriate for generating
such high frequency.
The Si4112 (derivative of Si4133) from www.silabs.com has an output
from 62 MHz to 1 GHz (and the part will work lower). They are
available from Digikey.
-Wallie
> I would like to generate 60 MHz to 100 MHz clock, in controlled step
of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
generate the same. Match functionality is inappropriate for generating
such high frequency.
The Si4112 (derivative of Si4133) from www.silabs.com has an output
from 62 MHz to 1 GHz (and the part will work lower). They are
available from Digikey.
-Wallie
Reply by ●June 12, 20052005-06-12
My requirement is basically to transmit data from one microcontroller
(LPC2138) to the other at 100MHz. Thus the clock generated must synchronize the
data. Si4112 has IF out relying upon its separate crystal. This may cause data
transition mismatch with driving clock. So its preferable to generate clock from
LPC2138. Please suggest any outcome.
Sudip
weverest3 <weverest@weve...> wrote:
--- In lpc2000@lpc2..., sudip nag <sudipnag1@y...> wrote:
> I would like to generate 60 MHz to 100 MHz clock, in controlled step
of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
generate the same. Match functionality is inappropriate for generating
such high frequency.
The Si4112 (derivative of Si4133) from www.silabs.com has an output
from 62 MHz to 1 GHz (and the part will work lower). They are
available from Digikey.
-Wallie
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Sudip
weverest3 <weverest@weve...> wrote:
--- In lpc2000@lpc2..., sudip nag <sudipnag1@y...> wrote:
> I would like to generate 60 MHz to 100 MHz clock, in controlled step
of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
generate the same. Match functionality is inappropriate for generating
such high frequency.
The Si4112 (derivative of Si4133) from www.silabs.com has an output
from 62 MHz to 1 GHz (and the part will work lower). They are
available from Digikey.
-Wallie
---------------------------------
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To
---------------------------------
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Reply by ●June 12, 20052005-06-12
At 05:25 PM 6/12/05 +0100, sudip nag wrote:
>My requirement is basically to transmit data from one microcontroller
>(LPC2138) to the other at 100MHz. Thus the clock generated must
>synchronize the data. Si4112 has IF out relying upon its separate crystal.
>This may cause data transition mismatch with driving clock. So its
>preferable to generate clock from LPC2138. Please suggest any outcome.
If you mean the LPC is to generate and clock out data at 100MHz it's not
going to happen. The LPC is only a 60MHz device.
BTW, where are you getting the 100MHz requirement? I took a quick look at
the Si4112 datasheet out of curiosity and sclk is restricted to a min of 40nS.
Robert
" 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
>My requirement is basically to transmit data from one microcontroller
>(LPC2138) to the other at 100MHz. Thus the clock generated must
>synchronize the data. Si4112 has IF out relying upon its separate crystal.
>This may cause data transition mismatch with driving clock. So its
>preferable to generate clock from LPC2138. Please suggest any outcome.
If you mean the LPC is to generate and clock out data at 100MHz it's not
going to happen. The LPC is only a 60MHz device.
BTW, where are you getting the 100MHz requirement? I took a quick look at
the Si4112 datasheet out of curiosity and sclk is restricted to a min of 40nS.
Robert
" 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
Reply by ●June 12, 20052005-06-12
sudip nag ha scritto:
>My requirement is basically to transmit data from one microcontroller (LPC2138) to the other at 100MHz. Thus the clock generated must synchronize the data. Si4112 has IF out relying upon its separate crystal. This may cause data transition mismatch with driving clock. So its preferable to generate clock from LPC2138. Please suggest any outcome. >
LPC2138 may have a clock lower then 60MHz so it is not possible to
generate directly from LPC2138 100MHz clock. Also if you need to
transfer data from a LPC2138 to a different mcu you may not do it at
100MHz. I think that also using assembler you may transmit to a fraction
of 60MHz may be burst data at 10MHz if your mcu hasn't to do anything else.
>Sudip
>
>weverest3 <weverest@weve...> wrote:
>--- In lpc2000@lpc2..., sudip nag <sudipnag1@y...> wrote: >>I would like to generate 60 MHz to 100 MHz clock, in controlled step
>>
>>
>of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
>generate the same. Match functionality is inappropriate for generating
>such high frequency.
>
>The Si4112 (derivative of Si4133) from www.silabs.com has an output
>from 62 MHz to 1 GHz (and the part will work lower). They are
>available from Digikey.
>
>-Wallie >
>
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>
> To >
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> Free antispam, antivirus and 1GB to save all your messages
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----------
>My requirement is basically to transmit data from one microcontroller (LPC2138) to the other at 100MHz. Thus the clock generated must synchronize the data. Si4112 has IF out relying upon its separate crystal. This may cause data transition mismatch with driving clock. So its preferable to generate clock from LPC2138. Please suggest any outcome. >
LPC2138 may have a clock lower then 60MHz so it is not possible to
generate directly from LPC2138 100MHz clock. Also if you need to
transfer data from a LPC2138 to a different mcu you may not do it at
100MHz. I think that also using assembler you may transmit to a fraction
of 60MHz may be burst data at 10MHz if your mcu hasn't to do anything else.
>Sudip
>
>weverest3 <weverest@weve...> wrote:
>--- In lpc2000@lpc2..., sudip nag <sudipnag1@y...> wrote: >>I would like to generate 60 MHz to 100 MHz clock, in controlled step
>>
>>
>of 1 MHz, with 50% duty cycle using LPC2138. Any suggestion how to
>generate the same. Match functionality is inappropriate for generating
>such high frequency.
>
>The Si4112 (derivative of Si4133) from www.silabs.com has an output
>from 62 MHz to 1 GHz (and the part will work lower). They are
>available from Digikey.
>
>-Wallie >
>
>---------------------------------
>Yahoo! Groups Links
>
> To >
>---------------------------------
> Free antispam, antivirus and 1GB to save all your messages
> Only in Yahoo! Mail: http://in.mail.yahoo.com >
>Yahoo! Groups Links >
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----------
Reply by ●June 13, 20052005-06-13
> sudip nag ha scritto:
>> My requirement is basically to transmit data from one
>> microcontroller (LPC2138) to the other at 100MHz. Thus the clock
>> generated must synchronize the data. Si4112 has IF out relying upon
>> its separate crystal. This may cause data transition mismatch with
>> driving clock. So its preferable to generate clock from LPC2138.
>> Please suggest any outcome.
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
Tele-IP Ltd. Email: bruce@bruc... Icq: #32015991
WWW: http://www.tele-ip.com VK3TJN
-------------------------------
>> My requirement is basically to transmit data from one
>> microcontroller (LPC2138) to the other at 100MHz. Thus the clock
>> generated must synchronize the data. Si4112 has IF out relying upon
>> its separate crystal. This may cause data transition mismatch with
>> driving clock. So its preferable to generate clock from LPC2138.
>> Please suggest any outcome.
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
Tele-IP Ltd. Email: bruce@bruc... Icq: #32015991
WWW: http://www.tele-ip.com VK3TJN
-------------------------------
Reply by ●June 14, 20052005-06-14
Hi,
My requirement is to interface Gigabit ethernet transceiver (>P0Mbps or >d mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency.
Please suggest.
Sudip
Bruce Paterson <bruce@bruc...> wrote:
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
Tele-IP Ltd. Email: bruce@bruc... Icq: #32015991
WWW: http://www.tele-ip.com VK3TJN
-------------------------------
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My requirement is to interface Gigabit ethernet transceiver (>P0Mbps or >d mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency.
Please suggest.
Sudip
Bruce Paterson <bruce@bruc...> wrote:
Without knowing your exact requirements, or whether a common multiple
can be found which lets you do all you need, why not run both chips from
the same crystal clock circuit ?
I'm assuming here you mean the data carrier is 100MHz, not the actual
data rate (which of course would not be possible from a slower LPC
unless you have external FIFO's or something).
--
Cheers,
Bruce
-------------------------------
/\\\/\\\/\\\ / / Bruce Paterson
/ \\\ \\\ \\\ / / Senior Design Engineer
/ /\\\/\\\/\\\/ / 8 Anzed Court, Mulgrave, Vic, 3170
/ / \\\ \\\ \\\ / PO Box 4112, Mulgrave, Vic, 3170, Australia
/ / \\\/\\\ \\\/ Ph: +61 3 8561 4232 Fax: +61 3 9560 9055
Tele-IP Ltd. Email: bruce@bruc... Icq: #32015991
WWW: http://www.tele-ip.com VK3TJN
-------------------------------
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Reply by ●June 14, 20052005-06-14
sudip nag ha scritto:
>Hi,
>My requirement is to interface Gigabit ethernet transceiver (>P0Mbps or >d mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency.
>Please suggest. I think you have to study better your problem. Actually you may transmit
and receive data burst at gigabit frequency WITHOUT to write data to the
transceiver at gigabit frequency; to do this also just for some data
burst you will need mcu with a clock frequency 10 or moretimes higher
then 64Mb. You have to choose a chip similar to CS8900 (that works at
10Mb) and then write the chip data buffers at lower frequency (you have
to check bus access timings dictated by the transceiver) so your
transceiver will send and receive bursts of 1 Gb data and your mcu may
rd/wr at its nominal bus frequency. This means that you will not e able
to send continuous data streams at 1Gb but this is normally accepted,
the only thing to measure is the response time from one packet reception
to packet handling and you have to manage the transceiver data buffers
(normally queue buffers) with one or more memory buffers/queue to have a
longer data burst handled at 1Gb.
>
>Sudip
>
>Bruce Paterson <bruce@bruc...> wrote:
>
>Without knowing your exact requirements, or whether a common multiple
>can be found which lets you do all you need, why not run both chips from
>the same crystal clock circuit ?
>I'm assuming here you mean the data carrier is 100MHz, not the actual
>data rate (which of course would not be possible from a slower LPC
>unless you have external FIFO's or something). --
>Hi,
>My requirement is to interface Gigabit ethernet transceiver (>P0Mbps or >d mega bytes per second). The data feeding technique is to supply 8 bit parallel data along with a clock that must exceed 64 MHz (64 mega bytes per second). Here I must synchronize each cycle of clock with data byte. So I need to generate such high clock frequency.
>Please suggest. I think you have to study better your problem. Actually you may transmit
and receive data burst at gigabit frequency WITHOUT to write data to the
transceiver at gigabit frequency; to do this also just for some data
burst you will need mcu with a clock frequency 10 or moretimes higher
then 64Mb. You have to choose a chip similar to CS8900 (that works at
10Mb) and then write the chip data buffers at lower frequency (you have
to check bus access timings dictated by the transceiver) so your
transceiver will send and receive bursts of 1 Gb data and your mcu may
rd/wr at its nominal bus frequency. This means that you will not e able
to send continuous data streams at 1Gb but this is normally accepted,
the only thing to measure is the response time from one packet reception
to packet handling and you have to manage the transceiver data buffers
(normally queue buffers) with one or more memory buffers/queue to have a
longer data burst handled at 1Gb.
>
>Sudip
>
>Bruce Paterson <bruce@bruc...> wrote:
>
>Without knowing your exact requirements, or whether a common multiple
>can be found which lets you do all you need, why not run both chips from
>the same crystal clock circuit ?
>I'm assuming here you mean the data carrier is 100MHz, not the actual
>data rate (which of course would not be possible from a slower LPC
>unless you have external FIFO's or something). --
Reply by ●June 14, 20052005-06-14
At 01:00 PM 6/14/05 +0100, sudip nag wrote:
>Hi,
>My requirement is to interface Gigabit ethernet transceiver (>P0Mbps
>or >d mega bytes per second). The data feeding technique is to supply 8
>bit parallel data along with a clock that must exceed 64 MHz (64 mega
>bytes per second). Here I must synchronize each cycle of clock with data
>byte. So I need to generate such high clock frequency.
>Please suggest.
What chip are you using that requires that kind of minimum?
It might be possible to burst at this rate with some sort of FIFO setup but
there is no way an LPC210xx is going to approach this speed.
Robert
" 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
>Hi,
>My requirement is to interface Gigabit ethernet transceiver (>P0Mbps
>or >d mega bytes per second). The data feeding technique is to supply 8
>bit parallel data along with a clock that must exceed 64 MHz (64 mega
>bytes per second). Here I must synchronize each cycle of clock with data
>byte. So I need to generate such high clock frequency.
>Please suggest.
What chip are you using that requires that kind of minimum?
It might be possible to burst at this rate with some sort of FIFO setup but
there is no way an LPC210xx is going to approach this speed.
Robert
" 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
