Hi,
for example TimerA generates every ms an interrupt. What happens when
during the execution of TimerA ISR an interrupt for port 1 is generated?
Is this Interrupt lost, or is it executed after TimerA ISR?
Do I have to enable GIE in TimerA ISR to ensure that the Irq for port 1
is not lost?
TIA,
Max
Interrupt occurs in ISR
Started by ●August 15, 2005
Reply by ●August 15, 20052005-08-15
When you go into an interrupt routine, the interrupts are automatically disabled, and the status register is saved on the stack. If an interrupt occurs during execution of your ISR, it is not lost, but it can only be executed after interrupts are enabled again. This will happen upon return of your current ISR, when the status register is restored from the stack. Of course, if servicing your current interrupt takes so long that 2 interrupts occur for, say , PORT 1, then the first one will be lost. You can avoid this situation by enabling interrupts within your ISR, BUT THIS IS A VERY DANGEROUS PRACTICE. It's much better to keep ISR short enough that the above situation does not arise. Michel --- In msp430@msp4..., agabuga@f... wrote: > Hi, > > for example TimerA generates every ms an interrupt. What happens when > during the execution of TimerA ISR an interrupt for port 1 is generated? > Is this Interrupt lost, or is it executed after TimerA ISR? > > Do I have to enable GIE in TimerA ISR to ensure that the Irq for port 1 > is not lost? > > TIA, > Max
Reply by ●August 16, 20052005-08-16
"michelqv" <michel@mich...> writes:
> When you go into an interrupt routine, the
interrupts are
> automatically disabled, and the status register is saved on the stack.
> If an interrupt occurs during execution of your ISR, it is not lost,
> but it can only be executed after interrupts are enabled again. [...]
Ok, thanks for pointing this out.
Does this mean that when I set GIE to enable Interrupts the first time,
that then Interrupts might be generated which had their origin a long
time before I set GIE?
Max
Reply by ●August 16, 20052005-08-16
----- Original Message ----- From: <agabuga@agab...> To: <msp430@msp4...> Sent: Tuesday, August 16, 2005 8:32 AM Subject: Re: [msp430] Re: Interrupt occurs in ISR "michelqv" <michel@mich...> writes: > When you go into an interrupt routine, the interrupts are > automatically disabled, and the status register is saved on the stack. > If an interrupt occurs during execution of your ISR, it is not lost, > but it can only be executed after interrupts are enabled again. [...] Ok, thanks for pointing this out. Does this mean that when I set GIE to enable Interrupts the first time, that then Interrupts might be generated which had their origin a long time before I set GIE? Max . Yahoo! Groups Links --- avast! Antivirus: Inbound message clean. Virus Database (VPS): 0533-0, 08/15/2005 Tested on: 8/16/2005 8:35:36 AM avast! - copyright (c) 1988-2005 ALWIL Software. http://www.avast.com
Reply by ●August 16, 20052005-08-16
Is this so? All interrupts are disabled ??? What you are saying is that, if the UART interrupts, no other interrupt even the ones with higher priority can interrupt the ISR??? Hmmmm... some how I do not think this is the case. Alex ----- Original Message ----- From: <agabuga@agab...> To: <msp430@msp4...> Sent: Tuesday, August 16, 2005 8:32 AM Subject: Re: [msp430] Re: Interrupt occurs in ISR "michelqv" <michel@mich...> writes: > When you go into an interrupt routine, the interrupts are > automatically disabled, and the status register is saved on the stack. > If an interrupt occurs during execution of your ISR, it is not lost, > but it can only be executed after interrupts are enabled again. [...] Ok, thanks for pointing this out. Does this mean that when I set GIE to enable Interrupts the first time, that then Interrupts might be generated which had their origin a long time before I set GIE? Max . Yahoo! Groups Links --- avast! Antivirus: Inbound message clean. Virus Database (VPS): 0533-0, 08/15/2005 Tested on: 8/16/2005 8:35:36 AM avast! - copyright (c) 1988-2005 ALWIL Software. http://www.avast.com
Reply by ●August 16, 20052005-08-16
Is this so? All interrupts are disabled ??? What you are saying is that, if the UART interrupts, no other interrupt even the ones with higher priority can interrupt the ISR??? Hmmmm... some how I do not think this is the case. Alex ----- Original Message ----- From: <agabuga@agab...> To: <msp430@msp4...> Sent: Tuesday, August 16, 2005 8:32 AM Subject: Re: [msp430] Re: Interrupt occurs in ISR "michelqv" <michel@mich...> writes: > When you go into an interrupt routine, the interrupts are > automatically disabled, and the status register is saved on the stack. > If an interrupt occurs during execution of your ISR, it is not lost, > but it can only be executed after interrupts are enabled again. [...] Ok, thanks for pointing this out. Does this mean that when I set GIE to enable Interrupts the first time, that then Interrupts might be generated which had their origin a long time before I set GIE? Max . Yahoo! Groups Links --- avast! Antivirus: Inbound message clean. Virus Database (VPS): 0533-0, 08/15/2005 Tested on: 8/16/2005 8:35:36 AM avast! - copyright (c) 1988-2005 ALWIL Software. http://www.avast.com
Reply by ●August 16, 20052005-08-16
>From: alex@alex... >Date: Tue Aug 16 07:36:16 CDT 2005 >Subject: Re: [msp430] Re: Interrupt occurs in ISR > >> When you go into an interrupt routine, the interrupts are >> automatically disabled, and the status register is saved on the stack. >> If an interrupt occurs during execution of your ISR, it is not lost, >> but it can only be executed after interrupts are enabled again. [...] > >Ok, thanks for pointing this out. > >Does this mean that when I set GIE to enable Interrupts the first time, >that then Interrupts might be generated which had their origin a long >time before I set GIE? Max, the short answer is yes. Any unit where the IFG (interrupt flag) bit is set will generate an interrupt because on is pending. These are generally masked by IE (interrupt enable) bits. You shouldn't need a massive set of bit clearing operations before your GIE, but be careful how you enable your various units which can produce interrupts, e.g. clear the IFG before setting the IE. Good Luck Rachel Adamec Norristown, PA
Reply by ●August 16, 20052005-08-16
Yes, since you have already enabled some peripheral interrupt. Each
peripheral like UART, timer, some I/O pins, etc, has an Interrupt Enable bit
that, if set prior to GIE, may allow the peripheral to generate an
interrupt. Then, when seting GIE first time you will have a first interrupt
servicing right after the set GIE instruction.
You can, in fact, set GIE inside an ISR to allow a higher priority interrupt
to take place. At least you can do that when using assembler because there
you have total control of what CPU is doing. In C I have no idea what
compilers do with registers but, I guess, all context is saved (what a waste
of time) and then you would have no problems there, too.
The only problem when enabling GIE inside an ISR would be a re-entry
interrupt source (i.e. the same interrupt source does interrupt again before
it's ISR is complete) where your stack pointer would run amok. (the
"re-entry" expression above may be wrong in English... deep in my
memory I
recall "re-entrant" but no sure, too, if it is correct).
Anyway, you may do almost everything on ISRs when you have total control of
your system. Sometimes it is better to have a long ISR instead of setting a
flag and then testing this flag along the main loop. If in the main loop you
have very long duration math loops that are not timing tight you may not be
able to put your flag test inside that loops (in order to keep execution
time faster) and then your ISR will need to do all the job inside the ISR.
It is all matters of planning your design.
-Augusto
-----Original Message-----
From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of
agabuga@agab...
Sent: Tuesday, August 16, 2005 9:32 AM
To: msp430@msp4...
Subject: Re: [msp430] Re: Interrupt occurs in ISR
"michelqv" <michel@mich...> writes:
> When you go into an interrupt routine, the
interrupts are
> automatically disabled, and the status register is saved on the stack.
> If an interrupt occurs during execution of your ISR, it is not lost,
> but it can only be executed after interrupts are enabled again. [...]
Ok, thanks for pointing this out.
Does this mean that when I set GIE to enable Interrupts the first time, that
then Interrupts might be generated which had their origin a long time before
I set GIE?
Max
.
Yahoo! Groups Links
--
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Checked by AVG Anti-Virus.
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Reply by ●August 16, 20052005-08-16
Augusto, GI has to be set to be able to vector to your ISR. Thus, once your ISR started, an interrupt with a higher priority can preempt the initial ISR, thus permitting ISR nesting without code intervention. One should dough be careful to make sure that the interrupted ISR can tolerate the delays introduced by the higher order Interrupt. Then, lets not forget NMI which can preempt all ISRs. This can be a nasty problem if one does not provide a gracious escape from Spurious NMIs. Alex ----- Original Message ----- From: "augusto einsfeldt" <aee@aee@...> To: <msp430@msp4...> Sent: Tuesday, August 16, 2005 9:56 AM Subject: RE: [msp430] Re: Interrupt occurs in ISR Yes, since you have already enabled some peripheral interrupt. Each peripheral like UART, timer, some I/O pins, etc, has an Interrupt Enable bit that, if set prior to GIE, may allow the peripheral to generate an interrupt. Then, when seting GIE first time you will have a first interrupt servicing right after the set GIE instruction. You can, in fact, set GIE inside an ISR to allow a higher priority interrupt to take place. At least you can do that when using assembler because there you have total control of what CPU is doing. In C I have no idea what compilers do with registers but, I guess, all context is saved (what a waste of time) and then you would have no problems there, too. The only problem when enabling GIE inside an ISR would be a re-entry interrupt source (i.e. the same interrupt source does interrupt again before it's ISR is complete) where your stack pointer would run amok. (the "re-entry" expression above may be wrong in English... deep in my memory I recall "re-entrant" but no sure, too, if it is correct). Anyway, you may do almost everything on ISRs when you have total control of your system. Sometimes it is better to have a long ISR instead of setting a flag and then testing this flag along the main loop. If in the main loop you have very long duration math loops that are not timing tight you may not be able to put your flag test inside that loops (in order to keep execution time faster) and then your ISR will need to do all the job inside the ISR. It is all matters of planning your design. -Augusto -----Original Message----- From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of agabuga@agab... Sent: Tuesday, August 16, 2005 9:32 AM To: msp430@msp4... Subject: Re: [msp430] Re: Interrupt occurs in ISR "michelqv" <michel@mich...> writes: > When you go into an interrupt routine, the interrupts are > automatically disabled, and the status register is saved on the stack. > If an interrupt occurs during execution of your ISR, it is not lost, > but it can only be executed after interrupts are enabled again. [...] Ok, thanks for pointing this out. Does this mean that when I set GIE to enable Interrupts the first time, that then Interrupts might be generated which had their origin a long time before I set GIE? Max . Yahoo! Groups Links -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.338 / Virus Database: 267.10.10/73 - Release Date: 15/8/2005 . Yahoo! Groups Links --- avast! Antivirus: Inbound message clean. Virus Database (VPS): 0533-0, 08/15/2005 Tested on: 8/16/2005 10:59:59 AM avast! - copyright (c) 1988-2005 ALWIL Software. http://www.avast.com
Reply by ●August 16, 20052005-08-16
True, but GI is AUTOMATICALLY disabled when you get into an ISR, so that you have to enable it "by hand" in your ISR if you want to allow interrupts there. Michel --- In msp430@msp4..., <alex@s...> wrote: > Augusto, > > GI has to be set to be able to vector to your ISR. Thus, once your ISR > started, an interrupt with a higher > priority can preempt the initial ISR, thus permitting ISR nesting without > code intervention. One should > dough be careful to make sure that the interrupted ISR can tolerate the > delays introduced by the > higher order Interrupt. > Then, lets not forget NMI which can preempt all ISRs. This can be a nasty > problem if one does > not provide a gracious escape from Spurious NMIs. > > Alex > > > ----- Original Message ----- > From: "augusto einsfeldt" <aee@t...> > To: <msp430@msp4...> > Sent: Tuesday, August 16, 2005 9:56 AM > Subject: RE: [msp430] Re: Interrupt occurs in ISR > > > Yes, since you have already enabled some peripheral interrupt. Each > peripheral like UART, timer, some I/O pins, etc, has an Interrupt Enable bit > that, if set prior to GIE, may allow the peripheral to generate an > interrupt. Then, when seting GIE first time you will have a first interrupt > servicing right after the set GIE instruction. > > You can, in fact, set GIE inside an ISR to allow a higher priority interrupt > to take place. At least you can do that when using assembler because there > you have total control of what CPU is doing. In C I have no idea what > compilers do with registers but, I guess, all context is saved (what a waste > of time) and then you would have no problems there, too. > The only problem when enabling GIE inside an ISR would be a re- entry > interrupt source (i.e. the same interrupt source does interrupt again before > it's ISR is complete) where your stack pointer would run amok. (the > "re-entry" expression above may be wrong in English... deep in my memory I > recall "re-entrant" but no sure, too, if it is correct). > > Anyway, you may do almost everything on ISRs when you have total control of > your system. Sometimes it is better to have a long ISR instead of setting a > flag and then testing this flag along the main loop. If in the main loop you > have very long duration math loops that are not timing tight you may not be > able to put your flag test inside that loops (in order to keep execution > time faster) and then your ISR will need to do all the job inside the ISR. > It is all matters of planning your design. > > -Augusto > > > -----Original Message----- > From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of > agabuga@f... > Sent: Tuesday, August 16, 2005 9:32 AM > To: msp430@msp4... > Subject: Re: [msp430] Re: Interrupt occurs in ISR > > > "michelqv" <michel@q...> writes: > > > When you go into an interrupt routine, the interrupts are > > automatically disabled, and the status register is saved on the stack. > > If an interrupt occurs during execution of your ISR, it is not lost, > > but it can only be executed after interrupts are enabled again. [...] > > Ok, thanks for pointing this out. > > Does this mean that when I set GIE to enable Interrupts the first time, that > then Interrupts might be generated which had their origin a long time before > I set GIE? > > Max > > > > > . > > > Yahoo! Groups Links > > > > > > > > > -- > No virus found in this outgoing message. > Checked by AVG Anti-Virus. > Version: 7.0.338 / Virus Database: 267.10.10/73 - Release Date: 15/8/2005 > > > > > > . > > > Yahoo! Groups Links > > > > > > > > > > --- > avast! Antivirus: Inbound message clean. > Virus Database (VPS): 0533-0, 08/15/2005 > Tested on: 8/16/2005 10:59:59 AM > avast! - copyright (c) 1988-2005 ALWIL Software. > http://www.avast.com
