# Determining the ADC sampling rate

Started by August 19, 2005
```Hello

If I set the MCU clock to run off 32kHz crystal and set up a 3 channel

1.) How do I determine the sampling rate?
2.) Varying the extended sampling time should affect the overal
sampling rate as well right?

Thanks
Jay

```
```There are two factors involved, however you clock the ADC12. These are
conversion time and sample time. tye conversion time is fixed, and you
get to vary the sample time in the ADC12CTL0 register. The conversion
time per channel is the sample time set in ADC12CTL0 SHTx bits. plus a
half cycle for tsync plus 13 cycles for conversion. Where the cycles are
based on ADC12CLK. If this is equal to 32khz then 3 channels will take
40.5 cycles plus 3 x SHTx. if this value is 4, for example the 3
conversions will take 52.5 cycles total.

Al

hc08jb8 wrote:

>Hello
>
>If I set the MCU clock to run off 32kHz crystal and set up a 3 channel
>
>1.) How do I determine the sampling rate?
>2.) Varying the extended sampling time should affect the overal
>sampling rate as well right?
>
>Thanks
>Jay
>
>
>
>
>
>.
>
>
>
>
>
>
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>
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>
>
>

```
```Thanks Al for the clear explaination :-)

Another quick question:-
1.) "The ADC12OSC, generated internally, is in the 5-MHz range, but
varies with
individual devices, supply voltage, and temperature" Does this
ADC12OSC operate independant of any clock/crystal on the circuitry,
i.e. when does this clock become active? when an ADC module is
enabled or only when a conversion is started?

Regds
Jay

--- In msp430@msp4..., Onestone <onestone@b...> wrote:
> There are two factors involved, however you clock
are
> conversion time and sample time. tye conversion
time is fixed, and
you
> get to vary the sample time in the ADC12CTL0
register. The
conversion
> time per channel is the sample time set in
plus a
> half cycle for tsync plus 13 cycles for
conversion. Where the
cycles are
> based on ADC12CLK. If this is equal to 32khz then
3 channels will
take
> 40.5 cycles plus 3 x SHTx. if this value is 4, for
example the 3
> conversions will take 52.5 cycles total.
>
> Al
>
> hc08jb8 wrote:
>
> >Hello
> >
> >If I set the MCU clock to run off 32kHz crystal and set up a 3
channel
> >
> >1.) How do I determine the sampling rate?
> >2.) Varying the extended sampling time should affect the overal
> >sampling rate as well right?
> >
> >Thanks
> >Jay
> >
> >
> >
> >
> >
> >.
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >

```
```It becomes enabled with the ADCON bit IIRC. If you want precise sampling
rates I would use the timer triggered modes of the ADC.

cheers

Al

hc08jb8 wrote:

>Thanks Al for the clear explaination :-)
>
>Another quick question:-
>1.) "The ADC12OSC, generated internally, is in the 5-MHz range, but
>varies with
>individual devices, supply voltage, and temperature" Does this
>ADC12OSC operate independant of any clock/crystal on the circuitry,
>i.e. when does this clock become active? when an ADC module is
>enabled or only when a conversion is started?
>
>Regds
>Jay
>
>
>--- In msp430@msp4..., Onestone <onestone@b...> wrote:
>
>
>>There are two factors involved, however you clock the ADC12. These
>>
>>
>are
>
>
>>conversion time and sample time. tye conversion time is fixed, and
>>
>>
>you
>
>
>>get to vary the sample time in the ADC12CTL0 register. The
>>
>>
>conversion
>
>
>>time per channel is the sample time set in ADC12CTL0 SHTx bits.
>>
>>
>plus a
>
>
>>half cycle for tsync plus 13 cycles for conversion. Where the
>>
>>
>cycles are
>
>
>>based on ADC12CLK. If this is equal to 32khz then 3 channels will
>>
>>
>take
>
>
>>40.5 cycles plus 3 x SHTx. if this value is 4, for example the 3
>>conversions will take 52.5 cycles total.
>>
>>Al
>>
>>hc08jb8 wrote:
>>
>>
>>
>>>Hello
>>>
>>>If I set the MCU clock to run off 32kHz crystal and set up a 3
>>>
>>>
>channel
>
>
>>>
>>>1.) How do I determine the sampling rate?
>>>2.) Varying the extended sampling time should affect the overal
>>>sampling rate as well right?
>>>
>>>Thanks
>>>Jay
>>>
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>
>
>
>
>
>
>.
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>