Not sure why this happens but when my TimerA ISR is vectored to, I can see that the TAIFG is clear. TAIV = 0; TACTL = 0101H TACCTL0, TACCTL1, TACCTL2 = 0010H TAR = 7FFEH TACCR0 = 7FFEH TACCR1, TACCR2 = 0 The timer is in mode 1 (MC_1). can any one explain why TAIFG is clear when entering the ISR ? TIA, Alex
TAIFG
Started by ●September 7, 2005
Reply by ●September 8, 20052005-09-08
To plagiate a member of this List :) Anyone? This is NOT an IAR question :) Alex ----- Original Message ----- From: <alex@alex...> To: <msp430@msp4...> Sent: Wednesday, September 07, 2005 7:48 PM Subject: [msp430] TAIFG > Not sure why this happens, but when my TimerA ISR is vectored to, I can see > that the TAIFG is clear. > TAIV = 0; > TACTL = 0101H > TACCTL0, TACCTL1, TACCTL2 = 0010H > TAR = 7FFEH > TACCR0 = 7FFEH > TACCR1, TACCR2 = 0 > > The timer is in mode 1 (MC_1). > > can any one explain why TAIFG is clear when entering the ISR ? > TIA, > > Alex > > > > > . > > > Yahoo! Groups Links > > > > > > > > > > --- > avast! Antivirus: Inbound message clean. > Virus Database (VPS): 0536-0, 09/05/2005 > Tested on: 9/7/2005 7:49:40 PM > avast! - copyright (c) 1988-2005 ALWIL Software. > http://www.avast.com > > >
Reply by ●September 8, 20052005-09-08
alex@alex... wrote:
> To plagiate a member of this List :)
>
> Anyone? This is NOT an IAR question :)
>
> Alex
>
>
>
> ----- Original Message -----
> From: <alex@alex...>
> To: <msp430@msp4...>
> Sent: Wednesday, September 07, 2005 7:48 PM
> Subject: [msp430] TAIFG
>
>
> > Not sure why this happens, but when my TimerA ISR is vectored to, I
can
> see
> > that the TAIFG is clear.
> > TAIV = 0;
> > TACTL = 0101H
> > TACCTL0, TACCTL1, TACCTL2 = 0010H
> > TAR = 7FFEH
> > TACCR0 = 7FFEH
> > TACCR1, TACCR2 = 0
> >
> > The timer is in mode 1 (MC_1).
> >
> > can any one explain why TAIFG is clear when entering the ISR ?
> > TIA,
> >
> > Alex
Alex,
From page 11-17 of the MSP430x1xx Family User's Guide:
"Any access, read or write, of the TAIV register automatically resets
the highest pending interrupt flag."
Hope this helps,
Greg Maki
Reply by ●September 8, 20052005-09-08
Alex,
Can't remember it now (and I'm traveling with no access to user guide)
but I belive TAIFG is resetd by hardware when the interrupt is serviced. So, you
should read it as zero.
The way to check would be to disable global interrupts and check TAIFG by
polling.
-Augusto
De:msp430@msp4...
Para:msp430@msp4...
Cia:
Data:Thu, 8 Sep 2005 12:44:55 -0400
Assunto:Fw: [msp430] TAIFG Take 2.
> To plagiate a member of this List :)
>
> Anyone? This is NOT an IAR question :)
>
> Alex
>
>
>
> ----- Original Message -----
> From:
> To:
> Sent: Wednesday, September 07, 2005 7:48 PM
> Subject: [msp430] TAIFG
>
>
> > Not sure why this happens, but when my TimerA ISR is vectored to, I
can
> see
> > that the TAIFG is clear.
> > TAIV = 0;
> > TACTL = 0101H
> > TACCTL0, TACCTL1, TACCTL2 = 0010H
> > TAR = 7FFEH
> > TACCR0 = 7FFEH
> > TACCR1, TACCR2 = 0
> >
> > The timer is in mode 1 (MC_1).
> >
> > can any one explain why TAIFG is clear when entering the ISR ?
> > TIA,
> >
> > Alex
> >
> >
> >
> >
> > .
> >
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > ---
> > avast! Antivirus: Inbound message clean.
> > Virus Database (VPS): 0536-0, 09/05/2005
> > Tested on: 9/7/2005 7:49:40 PM
> > avast! - copyright (c) 1988-2005 ALWIL Software.
> > http://www.avast.com
> >
> >
> >
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
Reply by ●September 8, 20052005-09-08
Greg, First instruction in the ISR is: i++; Just a dummy instruction where I set the break point. Once the breakpoint is stopping the program, the C-SPY is showing the Timer A registers as they have been captured at the time of the Break Point. There was no read or write by my program on any of the TimerA registers. This is where I see that TAIFG is clear. Is this normal ? Alex ----- Original Message ----- From: "Greg Maki" <gmaki@gmak...> To: <msp430@msp4...> Sent: Thursday, September 08, 2005 1:04 PM Subject: Re: Fw: [msp430] TAIFG Take 2. > alex@alex... wrote: > > To plagiate a member of this List :) > > > > Anyone? This is NOT an IAR question :) > > > > Alex > > > > > > > > ----- Original Message ----- > > From: <alex@alex...> > > To: <msp430@msp4...> > > Sent: Wednesday, September 07, 2005 7:48 PM > > Subject: [msp430] TAIFG > > > > > > > Not sure why this happens, but when my TimerA ISR is vectored to, I can > > see > > > that the TAIFG is clear. > > > TAIV = 0; > > > TACTL = 0101H > > > TACCTL0, TACCTL1, TACCTL2 = 0010H > > > TAR = 7FFEH > > > TACCR0 = 7FFEH > > > TACCR1, TACCR2 = 0 > > > > > > The timer is in mode 1 (MC_1). > > > > > > can any one explain why TAIFG is clear when entering the ISR ? > > > TIA, > > > > > > Alex > > Alex, > > From page 11-17 of the MSP430x1xx Family User's Guide: > > "Any access, read or write, of the TAIV register automatically resets > the highest pending interrupt flag." > > Hope this helps, > > Greg Maki > > > > . > > > Yahoo! Groups Links > > > > > > > > > > --- > avast! Antivirus: Inbound message clean. > Virus Database (VPS): 0536-0, 09/05/2005 > Tested on: 9/8/2005 1:10:03 PM > avast! - copyright (c) 1988-2005 ALWIL Software. > http://www.avast.com > > >
Reply by ●September 8, 20052005-09-08
Good to hear about you again Augusto. Hope your travels are all for pleasure :) The UM specifies the TAIFG as a "pending interrupt" flag. This implies, at least to me that once in the ISR you can check this flag to validate the interrupt. In turn this means that the flag should remain set until the first register read. This is not what I see in my program. I can see that TAR is equal to CCR0 and I infer that this is why the program vectored but I would like to have a confirmation. If TAIFG and TAIV are not visible during ISR, how do I know that I have not vectored because of a spurious IRQ? Alex ----- Original Message ----- From: "aee" <aee@aee@...> To: "msp430" <msp430@msp4...> Sent: Thursday, September 08, 2005 1:12 PM Subject: Re:Fw: [msp430] TAIFG Take 2. Alex, Can't remember it now (and I'm traveling with no access to user guide) but I belive TAIFG is resetd by hardware when the interrupt is serviced. So, you should read it as zero. The way to check would be to disable global interrupts and check TAIFG by polling. -Augusto De:msp430@msp4... Para:msp430@msp4... Cia: Data:Thu, 8 Sep 2005 12:44:55 -0400 Assunto:Fw: [msp430] TAIFG Take 2. > To plagiate a member of this List :) > > Anyone? This is NOT an IAR question :) > > Alex > > > > ----- Original Message ----- > From: > To: > Sent: Wednesday, September 07, 2005 7:48 PM > Subject: [msp430] TAIFG > > > > Not sure why this happens, but when my TimerA ISR is vectored to, I can > see > > that the TAIFG is clear. > > TAIV = 0; > > TACTL = 0101H > > TACCTL0, TACCTL1, TACCTL2 = 0010H > > TAR = 7FFEH > > TACCR0 = 7FFEH > > TACCR1, TACCR2 = 0 > > > > The timer is in mode 1 (MC_1). > > > > can any one explain why TAIFG is clear when entering the ISR ? > > TIA, > > > > Alex > > > > > > > > > > . > > > > > > Yahoo! Groups Links > > > > > > > > > > > > > > > > > > > > --- > > avast! Antivirus: Inbound message clean. > > Virus Database (VPS): 0536-0, 09/05/2005 > > Tested on: 9/7/2005 7:49:40 PM > > avast! - copyright (c) 1988-2005 ALWIL Software. > > http://www.avast.com > > > > > > > > > > > . > > > Yahoo! Groups Links > > > > > > . Yahoo! Groups Links --- avast! Antivirus: Inbound message clean. Virus Database (VPS): 0536-0, 09/05/2005 Tested on: 9/8/2005 1:16:51 PM avast! - copyright (c) 1988-2005 ALWIL Software. http://www.avast.com
Reply by ●September 8, 20052005-09-08
because CCR0 does NOT require access to TAIV, therefore it is reset as
soon as the ISR vector is taken, and before your i++. But you kill filed
me so you'll never ever know unless you read the manual properly.
Luv 'n kisses
Al
alex@alex... wrote:
>Good to hear about you again Augusto. Hope your
travels are all for pleasure
>:)
>The UM specifies the TAIFG as a "pending interrupt" flag. This
implies, at
>least to me
>that once in the ISR you can check this flag to validate the interrupt. In
>turn
>this means that the flag should remain set until the first register read.
>This is not what I see in my program.
>I can see that TAR is equal to CCR0 and I infer that this is why the program
>vectored
>but I would like to have a confirmation. If TAIFG and TAIV are not visible
>during ISR,
>how do I know that I have not vectored because of a spurious IRQ?
>
>Alex
>
>
>----- Original Message -----
>From: "aee" <aee@aee@...>
>To: "msp430" <msp430@msp4...>
>Sent: Thursday, September 08, 2005 1:12 PM
>Subject: Re:Fw: [msp430] TAIFG Take 2.
>
>
>Alex,
>Can't remember it now (and I'm traveling with no access to user
guide) but I
>belive TAIFG is resetd by hardware when the interrupt is serviced. So, you
>should read it as zero.
>The way to check would be to disable global interrupts and check TAIFG by
>polling.
>-Augusto
>
>De:msp430@msp4...
>
>Para:msp430@msp4...
>
>Cia:
>
>Data:Thu, 8 Sep 2005 12:44:55 -0400
>
>Assunto:Fw: [msp430] TAIFG Take 2.
>
>
>
>>To plagiate a member of this List :)
>>
>>Anyone? This is NOT an IAR question :)
>>
>>Alex
>>
>>
>>
>>----- Original Message -----
>>From:
>>To:
>>Sent: Wednesday, September 07, 2005 7:48 PM
>>Subject: [msp430] TAIFG
>>
>>
>>
>>
>>>Not sure why this happens, but when my TimerA ISR is vectored to, I
can
>>>
>>>
>>see
>>
>>
>>>that the TAIFG is clear.
>>>TAIV = 0;
>>>TACTL = 0101H
>>>TACCTL0, TACCTL1, TACCTL2 = 0010H
>>>TAR = 7FFEH
>>>TACCR0 = 7FFEH
>>>TACCR1, TACCR2 = 0
>>>
>>>The timer is in mode 1 (MC_1).
>>>
>>>can any one explain why TAIFG is clear when entering the ISR ?
>>>TIA,
>>>
>>>Alex
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>Yahoo! Groups Links
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>---
>>>avast! Antivirus: Inbound message clean.
>>>Virus Database (VPS): 0536-0, 09/05/2005
>>>Tested on: 9/7/2005 7:49:40 PM
>>>avast! - copyright (c) 1988-2005 ALWIL Software.
>>>http://www.avast.com
>>>
>>>
>>>
>>>
>>>
>>
>>
>>.
>>
>>
>>Yahoo! Groups Links
>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>.
>
>
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>---
>avast! Antivirus: Inbound message clean.
>Virus Database (VPS): 0536-0, 09/05/2005
>Tested on: 9/8/2005 1:16:51 PM
>avast! - copyright (c) 1988-2005 ALWIL Software.
>http://www.avast.com
>
>
>
>
>
>
>.
>
>
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
Reply by ●September 8, 20052005-09-08
alex@alex... wrote:
> Greg,
> First instruction in the ISR is:
> i++;
>
> Just a dummy instruction where I set the break point. Once the breakpoint
is
> stopping the
> program, the C-SPY is showing the Timer A registers as they have been
> captured at
> the time of the Break Point. There was no read or write by my program on
any
> of the TimerA registers. This is where I see that TAIFG is clear.
> Is this normal ?
> Alex
>
Alex,
I just tried it and it does look like the flag is cleared when entering
the interrupt, before TAIV is accessed. It does seem to contradict what
the user manual states.
Greg
Reply by ●September 8, 20052005-09-08
Yeah, TI is so cheap that they did not add a second CPU to monitor the first one and check that every step it takes is not "spurious". I'm sure that if the flag was not automatically reset upon entering the ISR, some people (who shall remain nameless) would complain that they have to waste an instruction to clear the flag in the ISR. Michel --- In msp430@msp4..., <alex@s...> wrote: > Good to hear about you again Augusto. Hope your travels are all for pleasure > :) > The UM specifies the TAIFG as a "pending interrupt" flag. This implies, at > least to me > that once in the ISR you can check this flag to validate the interrupt. In > turn > this means that the flag should remain set until the first register read. > This is not what I see in my program. > I can see that TAR is equal to CCR0 and I infer that this is why the program > vectored > but I would like to have a confirmation. If TAIFG and TAIV are not visible > during ISR, > how do I know that I have not vectored because of a spurious IRQ? > > Alex > > > ----- Original Message ----- > From: "aee" <aee@t...> > To: "msp430" <msp430@msp4...> > Sent: Thursday, September 08, 2005 1:12 PM > Subject: Re:Fw: [msp430] TAIFG Take 2. > > > Alex, > Can't remember it now (and I'm traveling with no access to user guide) but I > belive TAIFG is resetd by hardware when the interrupt is serviced. So, you > should read it as zero. > The way to check would be to disable global interrupts and check TAIFG by > polling. > -Augusto > > De:msp430@msp4... > > Para:msp430@msp4... > > Cia: > > Data:Thu, 8 Sep 2005 12:44:55 -0400 > > Assunto:Fw: [msp430] TAIFG Take 2. > > > To plagiate a member of this List :) > > > > Anyone? This is NOT an IAR question :) > > > > Alex > > > > > > > > ----- Original Message ----- > > From: > > To: > > Sent: Wednesday, September 07, 2005 7:48 PM > > Subject: [msp430] TAIFG > > > > > > > Not sure why this happens, but when my TimerA ISR is vectored to, I can > > see > > > that the TAIFG is clear. > > > TAIV = 0; > > > TACTL = 0101H > > > TACCTL0, TACCTL1, TACCTL2 = 0010H > > > TAR = 7FFEH > > > TACCR0 = 7FFEH > > > TACCR1, TACCR2 = 0 > > > > > > The timer is in mode 1 (MC_1). > > > > > > can any one explain why TAIFG is clear when entering the ISR ? > > > TIA, > > > > > > Alex > > > > > > > > > > > > > > > . > > > > > > > > > Yahoo! Groups Links > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --- > > > avast! Antivirus: Inbound message clean. > > > Virus Database (VPS): 0536-0, 09/05/2005 > > > Tested on: 9/7/2005 7:49:40 PM > > > avast! - copyright (c) 1988-2005 ALWIL Software. > > > http://www.avast.com > > > > > > > > > > > > > > > > > > > . > > > > > > Yahoo! Groups Links > > > > > > > > > > > > > > > > > > > > . > > > Yahoo! Groups Links > > > > > > > > > > --- > avast! Antivirus: Inbound message clean. > Virus Database (VPS): 0536-0, 09/05/2005 > Tested on: 9/8/2005 1:16:51 PM > avast! - copyright (c) 1988-2005 ALWIL Software. > http://www.avast.com
Reply by ●September 8, 20052005-09-08
hmmmm....I need to experiment a bit more ... But it is good to have an external confirmation that I do not dream :) Thanks, Greg Alex ----- Original Message ----- From: "Greg Maki" <gmaki@gmak...> To: <msp430@msp4...> Sent: Thursday, September 08, 2005 3:34 PM Subject: Re: Fw: [msp430] TAIFG Take 2. > alex@alex... wrote: > > Greg, > > First instruction in the ISR is: > > i++; > > > > Just a dummy instruction where I set the break point. Once the breakpoint is > > stopping the > > program, the C-SPY is showing the Timer A registers as they have been > > captured at > > the time of the Break Point. There was no read or write by my program on any > > of the TimerA registers. This is where I see that TAIFG is clear. > > Is this normal ? > > Alex > > > > Alex, > > I just tried it and it does look like the flag is cleared when entering > the interrupt, before TAIV is accessed. It does seem to contradict what > the user manual states. > > Greg > > > > . > > > Yahoo! Groups Links > > > > > > > > > > > --- > avast! Antivirus: Inbound message clean. > Virus Database (VPS): 0536-0, 09/05/2005 > Tested on: 9/8/2005 4:10:56 PM > avast! - copyright (c) 1988-2005 ALWIL Software. > http://www.avast.com > > >
