Please help me understand why the processor works with the DCOCLK,
if the MCLK is set to the LFXT1CLK:

   Tested on MSP430 F123, F1232, F1011
   LFXT1CLK = 8 MHz (I can see ACLK on P2.0)
   DCOCLK = 7xx KHz (Can be seen disconnecting JTAG, on P1.4)
   Program:

;------
            ORG         01000h                  ; Progam Start
;------
RESET       mov.w   #0A00h,SP               ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT

Oscil       bic     #OSCOFF,SR              ; Turn on osc.
            bis.b   #XTS,BCSCTL1            ; HF mode  (8 MHz)
            bic.b   #XT2OFF, BCSCTL1
            bis.b   #SELM1+SELM0,&BCSCTL2   ; Select MClk = LFXT1Clk
                                            ; DCOClk to SMClk by
definition

          //  bis.b   #DCOR,&BCSCTL2        ; External R; Lets me    
        see change in
                                              ;      P1.7 period

            bis.b   #BIT0, P2DIR            ; AClk out P2.0
            bis.b   #BIT0, P2SEL

            bis.b   #BIT7, P1DIR
;------
	; 10 cycle indirect look at the procesor's Clk = DCOCLK/10
Mainloop    bis.b   #BIT7,&P1OUT            ; P1.7 = 1
            bic.b   #BIT7,&P1OUT            ; P1.7 = 0
            jmp     Mainloop                ; Repeat
;------
;           Interrupt Vectors
;------
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET
            END

It seems your XT1 is not running fast enough and when you change MCLK to
XT1CLK the hardware senses an oscillator fault and get back to MCLK.
Then, few microseconds later the XT1 is ok (present at P2.0) but you
still need to select it as MCLK again and not doing this you keep DCO as
MCLK.
You should use the start-up scheme shown in the User's Manual, page 4-12
(or nearby according manual revision).
-Augusto


-----Mensagem original-----
De: msp430@msp4... [mailto:msp430@msp4...] Em nome de
totalneuro
Enviada em: domingo, 18 de setembro de 2005 21:36
Para: msp430@msp4...
Assunto: [msp430] Ignores: bis.b #SELM1+SELM0,&BCSCTL2



  Please help me understand why the processor works with the DCOCLK,
if the MCLK is set to the LFXT1CLK:

   Tested on MSP430 F123, F1232, F1011
   LFXT1CLK = 8 MHz (I can see ACLK on P2.0)
   DCOCLK = 7xx KHz (Can be seen disconnecting JTAG, on P1.4)
   Program:

;-----------------------------------
-------
            ORG         01000h                  ; Progam Start
;-----------------------------------
-------
RESET       mov.w   #0A00h,SP               ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT

Oscil       bic     #OSCOFF,SR              ; Turn on osc.
            bis.b   #XTS,BCSCTL1            ; HF mode  (8 MHz)
            bic.b   #XT2OFF, BCSCTL1
            bis.b   #SELM1+SELM0,&BCSCTL2   ; Select MClk = LFXT1Clk
                                            ; DCOClk to SMClk by
definition

          //  bis.b   #DCOR,&BCSCTL2        ; External R; Lets me    
        see change in
                                              ;      P1.7 period

            bis.b   #BIT0, P2DIR            ; AClk out P2.0
            bis.b   #BIT0, P2SEL

            bis.b   #BIT7, P1DIR
;-----------------------------------
-------
	; 10 cycle indirect look at the procesor's Clk = DCOCLK/10
Mainloop    bis.b   #BIT7,&P1OUT            ; P1.7 = 1
            bic.b   #BIT7,&P1OUT            ; P1.7 = 0
            jmp     Mainloop                ; Repeat
;-----------------------------------
-------
;           Interrupt Vectors
;-----------------------------------
-------
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET
            END








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