I'm trying to figure out what will be the maximum possible clock speed that can be used to clock the MSP430 onboard UART through the external UCLKx pin. To refine that a bit, I'm trying to figure out if I can achieve a higher baud rate than by using one of the various internal clocks to generate BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I don't understand where the 1/3 limit comes from, either, for that matter. a half hour of Googling really turned up no examples or commentary about using the external UCLK input with the UART. I also had a look at the list archives, and couldn't find anything. Any light you can shed on this will be appreciated. Mark
external uart clock
Started by ●March 1, 2006
Reply by ●March 1, 20062006-03-01
I'm trying to figure out what will be the maximum possible clock speed that can be used to clock the MSP430 onboard UART through the external UCLKx pin. To refine that a bit, I'm trying to figure out if I can achieve a higher baud rate than by using one of the various internal clocks to generate BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I don't understand where the 1/3 limit comes from, either, for that matter. a half hour of Googling really turned up no examples or commentary about using the external UCLK input with the UART. I also had a look at the list archives, and couldn't find anything. Any light you can shed on this will be appreciated. Mark
Reply by ●March 1, 20062006-03-01
Hi Mark, The 1/3 clock limit is due to the UART's sampling process. Traditional UARTs use a clock that is 16 times the actual baudrate. The main reason for this is that they want to create an easy way HW wise to (typically) take 3 samples instead of 1, and have the 2 extra samples very close (time wise) to the actual sampling moment. The 2 extra samples are + and - 1/16th of the clock, and majority voting is used to create a form of noise filtering. The MSP430 can process asynchronous streams up to 1/3 of the system clock, as opposed to 1/16th, there's still 3 samples with voting for each bit. An external USART clock should theoretically be able to run as fast as the system clock, but it depends on the USART implementation, its speed and how it interfaces onto the MCU's bus. Does that help ? B rgds Kris -----Original Message----- From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of Mark E. Skeels Sent: Thursday, 2 March 2006 6:42 AM To: msp430@msp4... Subject: [msp430] external uart clock I'm trying to figure out what will be the maximum possible clock speed that can be used to clock the MSP430 onboard UART through the external UCLKx pin. To refine that a bit, I'm trying to figure out if I can achieve a higher baud rate than by using one of the various internal clocks to generate BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I don't understand where the 1/3 limit comes from, either, for that matter. a half hour of Googling really turned up no examples or commentary about using the external UCLK input with the UART. I also had a look at the list archives, and couldn't find anything. Any light you can shed on this will be appreciated. Mark . Yahoo! Groups Links
Reply by ●March 1, 20062006-03-01
Kris,
Thanks for that explanation.
So then if I understand correctly, the external USART clock frequency
would still be limited by the uC clack, because of this sampling issue.
Is that correct?
Mark
Microbit wrote:
> Hi Mark,
>
> The 1/3 clock limit is due to the UART's sampling process.
> Traditional UARTs use a clock that is 16 times the actual baudrate.
> The main reason for this is that they want to create an easy way HW wise
> to (typically) take 3 samples instead of 1, and have the 2 extra
> samples very close
> (time wise) to the actual sampling moment.
> The 2 extra samples are + and - 1/16th of the clock, and majority voting
> is used to create a form of noise filtering.
> The MSP430 can process asynchronous streams up to 1/3 of the system
> clock, as
> opposed to 1/16th, there's still 3 samples with voting for each bit.
> An external USART clock should theoretically be able to run as fast as
> the system clock,
> but it depends on the USART implementation, its speed and how it
> interfaces onto the MCU's
> bus.
>
> Does that help ?
>
> B rgds
> Kris
>
> -----Original Message-----
> From: msp430@msp4... [mailto:msp430@msp4...] On Behalf
> Of Mark E. Skeels
> Sent: Thursday, 2 March 2006 6:42 AM
> To: msp430@msp4...
> Subject: [msp430] external uart clock
>
> I'm trying to figure out what will be the maximum possible clock speed
> that can be used to clock the MSP430 onboard UART through the external
> UCLKx pin.
>
> To refine that a bit, I'm trying to figure out if I can achieve a
higher
> baud rate than by using one of the various internal clocks to generate
> BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I
> don't understand where the 1/3 limit comes from, either, for that
matter.
>
> a half hour of Googling really turned up no examples or commentary about
> using the external UCLK input with the UART.
>
> I also had a look at the list archives, and couldn't find anything.
>
> Any light you can shed on this will be appreciated.
>
> Mark
>
>
>
>
>
> .
>
>
> >.
>
>
>
>
Reply by ●March 1, 20062006-03-01
Not necessarily,
The clock to the UART can't be more than 1/3 when internal.
Theoretically an external clock could be 3 times the system clock, but the issue
then
is whether the silicon (UART portion) will support the much higher clock.
I've never used external clock to async USART, or looked at the specs how
fast you can go.
But it seems common sense that the external clock can't be more than the
max rating of the
system clock IOW 8 MHz ????
This is a good question actually.
B rgds
Kris
-----Original Message-----
From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of Mark E. Skeels
Sent: Thursday, 2 March 2006 7:47 AM
To: msp430@msp4...
Subject: Re: [msp430] external uart clock
Kris,
Thanks for that explanation.
So then if I understand correctly, the external USART clock frequency
would still be limited by the uC clack, because of this sampling issue.
Is that correct?
Mark
Microbit wrote:
> Hi Mark,
>
> The 1/3 clock limit is due to the UART's sampling process.
> Traditional UARTs use a clock that is 16 times the actual baudrate.
> The main reason for this is that they want to create an easy way HW wise
> to (typically) take 3 samples instead of 1, and have the 2 extra
> samples very close
> (time wise) to the actual sampling moment.
> The 2 extra samples are + and - 1/16th of the clock, and majority voting
> is used to create a form of noise filtering.
> The MSP430 can process asynchronous streams up to 1/3 of the system
> clock, as
> opposed to 1/16th, there's still 3 samples with voting for each bit.
> An external USART clock should theoretically be able to run as fast as
> the system clock,
> but it depends on the USART implementation, its speed and how it
> interfaces onto the MCU's
> bus.
>
> Does that help ?
>
> B rgds
> Kris
>
> -----Original Message-----
> From: msp430@msp4... [mailto:msp430@msp4...] On Behalf
> Of Mark E. Skeels
> Sent: Thursday, 2 March 2006 6:42 AM
> To: msp430@msp4...
> Subject: [msp430] external uart clock
>
> I'm trying to figure out what will be the maximum possible clock speed
> that can be used to clock the MSP430 onboard UART through the external
> UCLKx pin.
>
> To refine that a bit, I'm trying to figure out if I can achieve a
higher
> baud rate than by using one of the various internal clocks to generate
> BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I
> don't understand where the 1/3 limit comes from, either, for that
matter.
>
> a half hour of Googling really turned up no examples or commentary about
> using the external UCLK input with the UART.
>
> I also had a look at the list archives, and couldn't find anything.
>
> Any light you can shed on this will be appreciated.
>
> Mark
>
>
>
>
>
> .
>
>
> >.
>
>
>
>
.
Yahoo! Groups Links
Reply by ●March 1, 20062006-03-01
Microbit wrote: > Not necessarily, > > The clock to the UART can't be more than 1/3 when internal. I think I understand this limitation.... > Theoretically an external clock could be 3 times the system clock, Don't understand this why this should be true, though.... > but the issue then > is whether the silicon (UART portion) will support the much higher clock. This makes sense... > I've never used external clock to async USART, or looked at the specs > how fast you can go. > But it seems common sense that the external clock can't be more than > the max rating of the > system clock IOW 8 MHz ???? This also makes sense. I still don't understand why the external UART clock would be limited to three times the system clock. You mean that if I run the Basic Clock Module, MCLK, SMCLK etc. at, say, 6 MHz, the external UART clock is limited to 2 MHz? Mark > > This is a good question actually. > > B rgds > Kris > > -----Original Message----- > From: msp430@msp4... [mailto:msp430@msp4...] On Behalf > Of Mark E. Skeels > Sent: Thursday, 2 March 2006 7:47 AM > To: msp430@msp4... > Subject: Re: [msp430] external uart clock > > Kris, > > Thanks for that explanation. > > So then if I understand correctly, the external USART clock frequency > would still be limited by the uC clack, because of this sampling issue. > Is that correct? > > Mark > > > Microbit wrote: > > > Hi Mark, > > > > The 1/3 clock limit is due to the UART's sampling process. > > Traditional UARTs use a clock that is 16 times the actual baudrate. > > The main reason for this is that they want to create an easy way HW wise > > to (typically) take 3 samples instead of 1, and have the 2 extra > > samples very close > > (time wise) to the actual sampling moment. > > The 2 extra samples are + and - 1/16th of the clock, and majority voting > > is used to create a form of noise filtering. > > The MSP430 can process asynchronous streams up to 1/3 of the system > > clock, as > > opposed to 1/16th, there's still 3 samples with voting for each bit. > > An external USART clock should theoretically be able to run as fast as > > the system clock, > > but it depends on the USART implementation, its speed and how it > > interfaces onto the MCU's > > bus. > > > > Does that help ? > > > > B rgds > > Kris > > > > -----Original Message----- > > From: msp430@msp4... [mailto:msp430@msp4...] On Behalf > > Of Mark E. Skeels > > Sent: Thursday, 2 March 2006 6:42 AM > > To: msp430@msp4... > > Subject: [msp430] external uart clock > > > > I'm trying to figure out what will be the maximum possible clock speed > > that can be used to clock the MSP430 onboard UART through the external > > UCLKx pin. > > > > To refine that a bit, I'm trying to figure out if I can achieve a higher > > baud rate than by using one of the various internal clocks to generate > > BRCLK, since BRCLK is limited to 1/3 of the source clock frequency. I > > don't understand where the 1/3 limit comes from, either, for that > matter. > > > > a half hour of Googling really turned up no examples or commentary about > > using the external UCLK input with the UART. > > > > I also had a look at the list archives, and couldn't find anything. > > > > Any light you can shed on this will be appreciated. > > > > Mark > > > > > > > > > > > > . > > > > > > >. > > > > > > > > > > > > . > > > >. > > > >
Reply by ●March 16, 20062006-03-16
Hi Mark, I overlooked this post, sorry. >-----Original Message----- >From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of Mark E. >Skeels >Sent: Thursday, 2 March 2006 8:14 AM >To: msp430@msp4... >Subject: Re: [msp430] external uart clock >> Theoretically an external clock could be 3 times the system clock, > >Don't understand this why this should be true, though.... The bottleneck is transferring the USART async data to/from CPU. If the CPU was running at 8 MHz, and it can sustain the UART's flow at max rate, then theoretically the external UART clock could be 24 MHz IOW 3 clocks / bit.... >> but the issue then >> is whether the silicon (UART portion) will support the much higher clock. > >This makes sense... Other bottlenecks of course being whether the USART can clock at eg. 24 MHz etc..... >I still don't understand why the external UART clock would be limited to >three times the system clock. You mean that if I run the Basic Clock >Module, MCLK, SMCLK etc. at, say, 6 MHz, the external UART clock is >limited to 2 MHz? No, in theory, if system clock is 6 MHz, you could ext clock the UART at 18 MHz.... In such a scenario you'd have to resort to DMA instead of ring buffer INTs, and the DMA Steals cycles of the CPU as well, so I think you'd have buffer overruns anyway, unless you Implement RTS/CTS style handshake. B rgds Kris
