Hi everybody,
Do you know the relationship between PDP-11 and MSP430 architecture?
Do you know how the MSP430 CPU core communicates with other modules?
(are the "communication between the CPU and modules" just like a
memory interface?)
I think ALU and memory unit are not triggered with clock.Because of
one-cycle register-to-register operations. Do you agree with me?

Anyway, I have almost completed my SystemC MSP430 CPU core design.Yo
can download it from my web site and you can try the executable file.
(www.salihzengin.com) The work is in the "project" part of my personal
web page. if you want to contribute to the work, you can contact me.
(I mean we can implement other parts of the
microcontroller:timers,DMA,multiplier,...)

Hi,

> I think ALU and memory unit are not triggered with
clock.Because of
> one-cycle register-to-register operations. Do you agree with me?

One cycle has 2 edges.
You can clock flip flops on separate edges, thus create a single cycle
operation.
Another option is "clock doubling".
Other RISCs will claim single cycle execution on the basis that a 2-pipeline
does a fetch
and store/execute at same time. Thus it "looks" like one cycle.
This is why eg. branches will incur 2 cycles, because the simple 2-stage
pipeline needs flushing
(ie. the new opcode needs fetching).
In that regard I liked the Super H's "delayed branching".

B rgds
Kris

Dear Kris,
What do you think about "R5<=R4+M[address]" this operation?
(reading a location from memory and adding this value to the R4,
lastly result is stored in R5)

Could it be possible to perform this operation within one cycle?
(without clock doubling like PICs)
if it could be, how?

Regards,
Salih

> In that regard I liked the Super H's "delayed
branching".

The HP 800 (Spectrum) machines always execute the instruction
after the branch - I guess this is what you mean by delayed
branching. But if I recall correctly, in the HP case, the branch
is detected in time before the *results* of the following
instruction are stored; the instruction gets nullified if the
branch is taken (unless it caused a trap, of course). The
compilers took advantage of this by re-ordering instructions.
Clever.

Hi Salih,
It is not possible.

Bahadir


----- Original Message ----- 
From: "minicikdev" <minicikdev@mini...>
To: <msp430@msp4...>
Sent: Thursday, April 20, 2006 9:36 AM
Subject: [msp430] Re: PDP-11 and MSP430


> Dear Kris,
> What do you think about "R5<=R4+M[address]" this
operation?
> (reading a location from memory and adding this value to the R4,
> lastly result is stored in R5)
> 
> Could it be possible to perform this operation within one cycle?
> (without clock doubling like PICs)
> if it could be, how?
> 
> Regards,
> Salih
> 
> 
> 
> 
> 
> .
> 
> 
> Yahoo! Groups Links
> 
> 
> 
> 
> 
> 
>

Split it down to simpler logic, similar to what a CPU needs to do:

- read address from instruction
- fetch content of M[address]
- add
- write

So there's at least 4 operations. Kris alludes to pipelining. With a 4 
stage pipelines, you can have the effect of single cycle execution if there 
are no branches etc.

Check out a computer architecture book for further info. You can't go wrong

with Paterson and Hennesy

At 11:36 PM 4/19/2006, you wrote:

>Dear Kris,
>What do you think about "R5<=R4+M[address]" this operation?
>(reading a location from memory and adding this value to the R4,
>lastly result is stored in R5)
>
>Could it be possible to perform this operation within one cycle?
>(without clock doubling like PICs)
>if it could be, how?
>
>Regards,
>Salih
>
>
>
>
>
>.
>
>
>
>
>
>SPONSORED LINKS
><http://groups.yahoo.com/gads?t=ms&k=Computer+internet+security&w1=Computer+internet+security&w2=Computer+internet+business&w3=Computer+internet+access&w4=Computer+internet+privacy+securities&w5=Computer+internet+help&w6=Texas+instruments&c=6&s7&.signZ9Q_Is69flQPlZteuKw>Computer

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// richard (This email is for mailing lists. To reach me directly, please 
use richard at imagecraft.com) 

More example....

ADD #0xABCD(R5),R6 => 3 cycles
ADD #0x1234(R5), #0xCDEF(R6) => 6 cycles

I think execution clock cycles include fetch state of next instruction.

Depending on these examples, could you guess how many pipeline-stages
MSP430 has?

Regards

You also need to look at how many words each instruction takes. Those 
addressing modes take additional words and each word will take a cycle to 
fetch.

At 12:43 AM 4/20/2006, you wrote:

>More example....
>
>ADD #0xABCD(R5),R6 => 3 cycles
>ADD #0x1234(R5), #0xCDEF(R6) => 6 cycles
>
>I think execution clock cycles include fetch state of next instruction.
>
>Depending on these examples, could you guess how many pipeline-stages
>MSP430 has?
>
>Regards
>
>----------

// richard (This email is for mailing lists. To reach me directly, please 
use richard at imagecraft.com) 

> You also need to look at how many words each
instruction takes. Those 
> addressing modes take additional words and each word will take a
cycle to 
> fetch.

 
So, take care of the needed memory locations for these instructions

More example....

ADD #0xABCD(R5),R6 => 3 cycles,2 word include op-code
ADD #0x1234(R5), #0xCDEF(R6) => 6 cycles, 3 word include op-code

I think execution clock cycles include fetch state of next instruction.

Depending on these examples, could you guess how many pipeline-stages
MSP430 has?

What about the RTL operations and their sequences?

minicikdev wrote:

> Do you know the relationship between PDP-11 and
MSP430 architecture?

They are pretty similar, on the machine instruction level, if I recall 
my MACRO 11 correctly.

I think the PDP-11 had eight 16 bit general purpose register. Compared 
to most other machines I had seen at the time, the "general purpose" 
part was great.

My guess is that PDP-11 influenced Motorolas 68000, which is turn 
influenced a lot of processors, including the MSP430.


On the other hand, I remember when I and a few friend got our school to 
buy an old PDP-11 (/60? /70?) and we had to carry the cabinets (not to 
mention the washing-machine-sized disk drives). So from this point of 
view the "architecture" of a PDP-11 is different, to say the least, 
compared to a MSP430. This was in the mid- late- eighties, by the way...

     -- Anders
-- 
Disclaimer: Opinions expressed in this posting are strictly my own and
not necessarily those of my employer.