I am new to the MSP430 and the MSP430 way to do things. So if I am doing
something stupid let me know.

I designed a board with a MSP430F1610. It has a 32,768 Hz clock on the
first clock port used for the ACLK, and a 3.6864 MHz clock for the two
UARTs (SMCLK).
The processor instructions will run off of the DCO. (That is the plan at
the moment.)

I have a function written in assembler, that I will call from C using
the free IAR 4K C Compiler to change the DCO clock.

PUBLIC DCO_Low
DCO_Low
bic.b #OFIE,&IE1
mov.b #XTS+RSEL0,&BCSCTL1
mov.b #SELS,&BCSCTL2
DCO_LowA
bic.b #OFIFG,&IFG1
mov #0xFF,R4
DCO_LowB
dec R4
jnz DCO_LowB
bit.b #OFIFG,&IFG1
jnz DCO_LowA
bis.b #OFIE,&IE1
add.w #4,0x0(SP)
ret

It looks from the debugger that it calls O.K. and returns O.K. The
problem is that OFIFG bit in IFG1 never clears. As soon as I clear it
with
bic.b #OFIFG,&IFG1

The debugger says it is still 1. As a result it stays stuck in the loop.

I do not know where to look for the answer. The status register (SR) is
5.

Any ideas anybody?

Kip
--
Kipton Moravec

Start a New Thread

I think instead of "mov.b #XTS+RSEL0,&BCSCTL1",
you should use "mov.b #RSEL0,&BCSCTL1".

Also, you should move "mov.b #SELS,&BCSCTL2"
to the very end before "ret" and after you
made sure that XT2 is stable.

But the above two points do not explain why
XT2 fails. May be the crystal is not right?
Do you have caps? Take a closer look at the
hardware.

--- In m..., Kipton Moravec wrote:
>
> I am new to the MSP430 and the MSP430 way to do things. So if I am
doing
> something stupid let me know.
>
> I designed a board with a MSP430F1610. It has a 32,768 Hz clock on
the
> first clock port used for the ACLK, and a 3.6864 MHz clock for the
two
> UARTs (SMCLK).
> The processor instructions will run off of the DCO. (That is the
plan at
> the moment.)
>
> I have a function written in assembler, that I will call from C
using
> the free IAR 4K C Compiler to change the DCO clock.
>
> PUBLIC DCO_Low
> DCO_Low
> bic.b #OFIE,&IE1
> mov.b #XTS+RSEL0,&BCSCTL1
> mov.b #SELS,&BCSCTL2
> DCO_LowA
> bic.b #OFIFG,&IFG1
> mov #0xFF,R4
> DCO_LowB
> dec R4
> jnz DCO_LowB
> bit.b #OFIFG,&IFG1
> jnz DCO_LowA
> bis.b #OFIE,&IE1
> add.w #4,0x0(SP)
> ret
>
> It looks from the debugger that it calls O.K. and returns O.K. The
> problem is that OFIFG bit in IFG1 never clears. As soon as I clear
it
> with
> bic.b #OFIFG,&IFG1
>
> The debugger says it is still 1. As a result it stays stuck in the
loop.
>
> I do not know where to look for the answer. The status register
(SR) is
> 5.
>
> Any ideas anybody?
>
> Kip
> --
> Kipton Moravec
Start a New Thread