Hi to all
I have been stuck up with the problem of sampling an input signal at
8000 times per second on a MSP430F169
What i do is generate an interrupt at 0.125 miil second ( equivalent
to 8000 triggers per second) and i run a ISR routine where a/d
conversion is performed and transferred to DAC .
My SMCLK and MCLK are 2MHz and SMCLK is used as ADC12CLK.When i see
the output the frequency is very much reduced. I have to increase the
sampling rate to ensure no frequency reduction. The conversion time is
longer than what is computed for ADC12CLK.
Can anyone give me a diection on to fix the bug.
A/D conversion
Started by ●March 22, 2007
Reply by ●March 22, 20072007-03-22
Are you sure MCLK and SMCLK are 2MHz? You can put them on Port 5 pins
and use an oscilloscope to check them.
Even if you got 2MHz, there are only 250 clock cycles between your
desired 8kHz sampling rate. Is 250 cycles enough for the CPU and the
ADC to handle one sample? You may want to change the clock rate to 4MHz
while keep your sampling rate at 8kHz.
--- In m..., "hawkran" wrote:
>
> Hi to all
>
> I have been stuck up with the problem of sampling an input signal at
> 8000 times per second on a MSP430F169
>
> What i do is generate an interrupt at 0.125 miil second ( equivalent
> to 8000 triggers per second) and i run a ISR routine where a/d
> conversion is performed and transferred to DAC .
>
> My SMCLK and MCLK are 2MHz and SMCLK is used as ADC12CLK.When i see
> the output the frequency is very much reduced. I have to increase the
> sampling rate to ensure no frequency reduction. The conversion time is
> longer than what is computed for ADC12CLK.
>
> Can anyone give me a diection on to fix the bug.
>
and use an oscilloscope to check them.
Even if you got 2MHz, there are only 250 clock cycles between your
desired 8kHz sampling rate. Is 250 cycles enough for the CPU and the
ADC to handle one sample? You may want to change the clock rate to 4MHz
while keep your sampling rate at 8kHz.
--- In m..., "hawkran" wrote:
>
> Hi to all
>
> I have been stuck up with the problem of sampling an input signal at
> 8000 times per second on a MSP430F169
>
> What i do is generate an interrupt at 0.125 miil second ( equivalent
> to 8000 triggers per second) and i run a ISR routine where a/d
> conversion is performed and transferred to DAC .
>
> My SMCLK and MCLK are 2MHz and SMCLK is used as ADC12CLK.When i see
> the output the frequency is very much reduced. I have to increase the
> sampling rate to ensure no frequency reduction. The conversion time is
> longer than what is computed for ADC12CLK.
>
> Can anyone give me a diection on to fix the bug.
>
Reply by ●March 23, 20072007-03-23
This is a great question to illustrate what you can do with the '169 et
al.
At high conversion rates you don't use an isr to do all the work.
Instead set up Timer_A3 or Timer_B7 to generate an interrupt at the
appropriate rate (8kHz in this case) and trigger the ADC conversion
off this timer while ensuring the cpu is in some low power mode,
preferably LPM3, which reduces noise on the ADC conversion. To use
LPM3 means you have to clock the timer from (typically) the 32.768kHz
crystal, which is ok for 8kHz, since that clock stays alive during
LPM3. So now you have the ADC doing conversions at 8kHz, no cpu
involved, but remember to also set the local ADC oscillator mode.
If no data manipulation is required, hook up a DMA channel -
triggered by the ADC completion - to transfer the result directly to
the DAC. Note again no interrupts or cpu time required. If data
manipulation is required, such as scaling or averaging, arrange the
ADC to interrupt when the required number of readings are ready so
that the cpu can manipulate the data and transfer it to the DAC
before the next ADC conversion takes place, since you want the cpu to
be asleep each time a reading is taken (to minimise noise). You can
get fancy here, and have one DMA channel buffer the ADC reading into
an input buffer, and a second DMA channel transfer the processed data
into the DAC. The first DMA channel can be triggered either by one of
the Timer_A3 channels, or by the ADC completion. The second DMA
channel can be triggered by a Timer_A3 channel. That last step - in
fact both steps (Timer_A3 channel 0 triggers the ADC and Timer_A3
channel 1 triggers the DMA into the DAC) is important, because now
the precise moment at which the ADC reading is taken and the precise
moment at which the DAC is latched is defined in hardware, and not by
software in an isr. This matters because using an isr will result in
jitter in the input and output timing, which is often significant.
The ADC jitter lowers the PSRR (Power Supply Rejection Ratio,
typically you want to ignore 50Hz or 60Hz and so sample at specific
times, and the DAC jitter increases the output distortion of a changing signal.
Now you have this setup:
Timer_A3:0 triggers the ADC
ADC completion triggers DMA:0
DMA:0 completion triggers the cpu isr - noise starts here
cpu isr completes work on data then sleeps - noise stops here
Timer_A3:2 or Timer_B7:2 or previous cpu isr triggers DMA:1
Timer_A3:1 or Timer_B7:2 or DMA triggers DAC
Note you can get clever, and save even more power:
Timer_A3:n or Timer_B7:n generates an interrupt - noise starts here
cpu isr powers up input circuit then sleeps - noise stops here
.. time to allow the input circuit to turn on ...
Timer_A3:0 triggers the ADC
ADC completion triggers DMA:0
DMA:0 completion triggers the cpu isr - noise starts here
cpu powers down the input circuit
cpu isr completes work on data then sleeps - noise stops here
Timer_A3:2 or Timer_B7:2 or previous cpu isr triggers DMA:1
DMA:1 transfers result to DAC
Timer_A3:1 or Timer_B7:2 or DMA triggers DAC
A lot depends on just what translation of the data between ADC and
DAC you are looking for, and since the ADC has it's own DMA of sorts
you don't even have to use a true DMA channel, particularly if you
are using two DMA channels already for serial Tx and Rx. (Why would
you be doing that? Because it saves power since DMA is much faster
than byte interrupts on serial port packet transfers).
Remember that the DMA works by stealing two clock cycles from the cpu
for each transfer, but each pair of stolen cycles can only start at
the completion of a complete cpu instruction. Therefore you do not
want the cpu executing variable length instructions around the time
the DMA is going to trigger. This is another reason to keep the cpu
in LPM3, since then you are sure that this is the case. Of course you
can just trigger the DAC from a timer channel, then not worry about
whether the cpu was awake at the time of the DMA, just ensure the DMA
takes place before it's time for the timer to latch the DAC output.
Hugh
At 02:25 AM 3/22/2007, you wrote:
Hi to all
I have been stuck up with the problem of sampling an input signal at
8000 times per second on a MSP430F169
What i do is generate an interrupt at 0.125 miil second ( equivalent
to 8000 triggers per second) and i run a ISR routine where a/d
conversion is performed and transferred to DAC .
My SMCLK and MCLK are 2MHz and SMCLK is used as ADC12CLK.When i see
the output the frequency is very much reduced. I have to increase the
sampling rate to ensure no frequency reduction. The conversion time is
longer than what is computed for ADC12CLK.
Can anyone give me a diection on to fix the bug.
At high conversion rates you don't use an isr to do all the work.
Instead set up Timer_A3 or Timer_B7 to generate an interrupt at the
appropriate rate (8kHz in this case) and trigger the ADC conversion
off this timer while ensuring the cpu is in some low power mode,
preferably LPM3, which reduces noise on the ADC conversion. To use
LPM3 means you have to clock the timer from (typically) the 32.768kHz
crystal, which is ok for 8kHz, since that clock stays alive during
LPM3. So now you have the ADC doing conversions at 8kHz, no cpu
involved, but remember to also set the local ADC oscillator mode.
If no data manipulation is required, hook up a DMA channel -
triggered by the ADC completion - to transfer the result directly to
the DAC. Note again no interrupts or cpu time required. If data
manipulation is required, such as scaling or averaging, arrange the
ADC to interrupt when the required number of readings are ready so
that the cpu can manipulate the data and transfer it to the DAC
before the next ADC conversion takes place, since you want the cpu to
be asleep each time a reading is taken (to minimise noise). You can
get fancy here, and have one DMA channel buffer the ADC reading into
an input buffer, and a second DMA channel transfer the processed data
into the DAC. The first DMA channel can be triggered either by one of
the Timer_A3 channels, or by the ADC completion. The second DMA
channel can be triggered by a Timer_A3 channel. That last step - in
fact both steps (Timer_A3 channel 0 triggers the ADC and Timer_A3
channel 1 triggers the DMA into the DAC) is important, because now
the precise moment at which the ADC reading is taken and the precise
moment at which the DAC is latched is defined in hardware, and not by
software in an isr. This matters because using an isr will result in
jitter in the input and output timing, which is often significant.
The ADC jitter lowers the PSRR (Power Supply Rejection Ratio,
typically you want to ignore 50Hz or 60Hz and so sample at specific
times, and the DAC jitter increases the output distortion of a changing signal.
Now you have this setup:
Timer_A3:0 triggers the ADC
ADC completion triggers DMA:0
DMA:0 completion triggers the cpu isr - noise starts here
cpu isr completes work on data then sleeps - noise stops here
Timer_A3:2 or Timer_B7:2 or previous cpu isr triggers DMA:1
Timer_A3:1 or Timer_B7:2 or DMA triggers DAC
Note you can get clever, and save even more power:
Timer_A3:n or Timer_B7:n generates an interrupt - noise starts here
cpu isr powers up input circuit then sleeps - noise stops here
.. time to allow the input circuit to turn on ...
Timer_A3:0 triggers the ADC
ADC completion triggers DMA:0
DMA:0 completion triggers the cpu isr - noise starts here
cpu powers down the input circuit
cpu isr completes work on data then sleeps - noise stops here
Timer_A3:2 or Timer_B7:2 or previous cpu isr triggers DMA:1
DMA:1 transfers result to DAC
Timer_A3:1 or Timer_B7:2 or DMA triggers DAC
A lot depends on just what translation of the data between ADC and
DAC you are looking for, and since the ADC has it's own DMA of sorts
you don't even have to use a true DMA channel, particularly if you
are using two DMA channels already for serial Tx and Rx. (Why would
you be doing that? Because it saves power since DMA is much faster
than byte interrupts on serial port packet transfers).
Remember that the DMA works by stealing two clock cycles from the cpu
for each transfer, but each pair of stolen cycles can only start at
the completion of a complete cpu instruction. Therefore you do not
want the cpu executing variable length instructions around the time
the DMA is going to trigger. This is another reason to keep the cpu
in LPM3, since then you are sure that this is the case. Of course you
can just trigger the DAC from a timer channel, then not worry about
whether the cpu was awake at the time of the DMA, just ensure the DMA
takes place before it's time for the timer to latch the DAC output.
Hugh
At 02:25 AM 3/22/2007, you wrote:
Hi to all
I have been stuck up with the problem of sampling an input signal at
8000 times per second on a MSP430F169
What i do is generate an interrupt at 0.125 miil second ( equivalent
to 8000 triggers per second) and i run a ISR routine where a/d
conversion is performed and transferred to DAC .
My SMCLK and MCLK are 2MHz and SMCLK is used as ADC12CLK.When i see
the output the frequency is very much reduced. I have to increase the
sampling rate to ensure no frequency reduction. The conversion time is
longer than what is computed for ADC12CLK.
Can anyone give me a diection on to fix the bug.
Reply by ●March 23, 20072007-03-23
Hello
Yes there are 250 clocks available between 2
samples.As per the specs ADC block will take 13 clocks
for conversion+ 1 clock for sync+sampling time set(
we set it for 8 clocks) . This means it should take 22
clocks for one conversion. Is it correct? If it is
correct i think the time has enough cushion to sample
8000 sample per second.Or is there anything more to
it.
--- old_cow_yellow wrote:
> Are you sure MCLK and SMCLK are 2MHz? You can put
> them on Port 5 pins
> and use an oscilloscope to check them.
>
> Even if you got 2MHz, there are only 250 clock
> cycles between your
> desired 8kHz sampling rate. Is 250 cycles enough for
> the CPU and the
> ADC to handle one sample? You may want to change the
> clock rate to 4MHz
> while keep your sampling rate at 8kHz.
>
> --- In m..., "hawkran"
> wrote:
> >
> > Hi to all
> >
> > I have been stuck up with the problem of sampling
> an input signal at
> > 8000 times per second on a MSP430F169
> >
> > What i do is generate an interrupt at 0.125 miil
> second ( equivalent
> > to 8000 triggers per second) and i run a ISR
> routine where a/d
> > conversion is performed and transferred to DAC .
> >
> > My SMCLK and MCLK are 2MHz and SMCLK is used as
> ADC12CLK.When i see
> > the output the frequency is very much reduced. I
> have to increase the
> > sampling rate to ensure no frequency reduction.
> The conversion time is
> > longer than what is computed for ADC12CLK.
> >
> > Can anyone give me a diection on to fix the bug.
>
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Yes there are 250 clocks available between 2
samples.As per the specs ADC block will take 13 clocks
for conversion+ 1 clock for sync+sampling time set(
we set it for 8 clocks) . This means it should take 22
clocks for one conversion. Is it correct? If it is
correct i think the time has enough cushion to sample
8000 sample per second.Or is there anything more to
it.
--- old_cow_yellow wrote:
> Are you sure MCLK and SMCLK are 2MHz? You can put
> them on Port 5 pins
> and use an oscilloscope to check them.
>
> Even if you got 2MHz, there are only 250 clock
> cycles between your
> desired 8kHz sampling rate. Is 250 cycles enough for
> the CPU and the
> ADC to handle one sample? You may want to change the
> clock rate to 4MHz
> while keep your sampling rate at 8kHz.
>
> --- In m..., "hawkran"
> wrote:
> >
> > Hi to all
> >
> > I have been stuck up with the problem of sampling
> an input signal at
> > 8000 times per second on a MSP430F169
> >
> > What i do is generate an interrupt at 0.125 miil
> second ( equivalent
> > to 8000 triggers per second) and i run a ISR
> routine where a/d
> > conversion is performed and transferred to DAC .
> >
> > My SMCLK and MCLK are 2MHz and SMCLK is used as
> ADC12CLK.When i see
> > the output the frequency is very much reduced. I
> have to increase the
> > sampling rate to ensure no frequency reduction.
> The conversion time is
> > longer than what is computed for ADC12CLK.
> >
> > Can anyone give me a diection on to fix the bug.
>
__________________________________________________________
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http://in.answers.yahoo.com/
