Hi all,
After a long battle i got the high frequency clock (8MHz)
from LFXT1 produced at P5.6(Aclk). I am still not able to
configure MCLK = LFXT1 and MCLK still operates from DCO.
The only thing now remaining besides configuring clock
registers as below is setting SCG0 bit in SR.Has anyone
gone through this pain?? I want to confirm that you "can"
write to SR. I am using Imagecraft compiler and header file
has no definition for Status register, though SCG0 is defined
as #define SCG0 (0x0040)
Does anyone know how to write to SR or turn SCG0 =1 or
any trick around this situation....Thanks in advance...

DCOCTL=0x00; //0X40
BCSCTL1=0xC0;//XT2OFF , LFXT1 in High frequency mode (0X87 for DCO)//
BCSCTL2=0xC0; //LFXT1 Clock source & MCLK = LFXT1/1 (0X40)// Start a New Thread

europus wrote:
> Hi all,
> After a long battle i got the high frequency clock (8MHz)
> from LFXT1 produced at P5.6(Aclk). I am still not able to
> configure MCLK = LFXT1 and MCLK still operates from DCO.
> The only thing now remaining besides configuring clock
> registers as below is setting SCG0 bit in SR.Has anyone
> gone through this pain?? I want to confirm that you "can"
> write to SR. I am using Imagecraft compiler and header file
> has no definition for Status register, though SCG0 is defined
> as #define SCG0 (0x0040)
> Does anyone know how to write to SR or turn SCG0 =1 or
> any trick around this situation....Thanks in advance...
>

Include the inmsp.h or in430.h header file (or similar file in Imagecraft).

There should be an intrinsic like _BIS_SR() or __bis_SR_register().

HTH.
KF
> DCOCTL=0x00; //0X40
> BCSCTL1=0xC0;//XT2OFF , LFXT1 in High frequency mode (0X87 for DCO)//
> BCSCTL2=0xC0; //LFXT1 Clock source & MCLK = LFXT1/1 (0X40)//
> Start a New Thread

You need to clear OFIFG **and make sure that it stays clear** before
you use the 8MHz clock as MCLK.

If you clear OFIFG when the 8MHz clock is not stable yet, OFIFG will
stay cleared for some duration of time, but it will become set again
later.

Did you try to clear OFIFG?

TI provided examples of how you can do it correctly. But the
c-compiler may remove the delay and that makes it incorrect. Check the
compiled code.

You do not need to set the SCGO bit in SR register. If you do need to
do it, while do you use a c-compiler that does not let you do it? You
use tools to save your own effort. But you seem to get the opposite
result and wasted a lot of effort.

--- In m..., "europus" wrote:
>
> Hi all,
> After a long battle i got the high frequency clock (8MHz)
> from LFXT1 produced at P5.6(Aclk). I am still not able to
> configure MCLK = LFXT1 and MCLK still operates from DCO.
> The only thing now remaining besides configuring clock
> registers as below is setting SCG0 bit in SR.Has anyone
> gone through this pain?? I want to confirm that you "can"
> write to SR. I am using Imagecraft compiler and header file
> has no definition for Status register, though SCG0 is defined
> as #define SCG0 (0x0040)
> Does anyone know how to write to SR or turn SCG0 =1 or
> any trick around this situation....Thanks in advance...
>
> DCOCTL=0x00; //0X40
> BCSCTL1=0xC0;//XT2OFF , LFXT1 in High frequency mode (0X87 for DCO)//
> BCSCTL2=0xC0; //LFXT1 Clock source & MCLK = LFXT1/1 (0X40)//
> Start a New Thread

Thanks Leong....I found the file and i update the file but still can't get the DCO to stop interfering. I checked by applying a square wave signal from my signal generator and the
bit timings do not vary !!! i.e I have flashed a program that pulls certain line high and then low
in next instruction. And this line is showing me 400uSec Timing which does not change
with change in clock frequency :(.......any help will be appreciated....thanks

KF Leong wrote:
europus wrote:
> Hi all,
> After a long battle i got the high frequency clock (8MHz)
> from LFXT1 produced at P5.6(Aclk). I am still not able to
> configure MCLK = LFXT1 and MCLK still operates from DCO.
> The only thing now remaining besides configuring clock
> registers as below is setting SCG0 bit in SR.Has anyone
> gone through this pain?? I want to confirm that you "can"
> write to SR. I am using Imagecraft compiler and header file
> has no definition for Status register, though SCG0 is defined
> as #define SCG0 (0x0040)
> Does anyone know how to write to SR or turn SCG0 =1 or
> any trick around this situation....Thanks in advance...
>

Include the inmsp.h or in430.h header file (or similar file in Imagecraft).

There should be an intrinsic like _BIS_SR() or __bis_SR_register().

HTH.
KF

> DCOCTL=0x00; //0X40
> BCSCTL1=0xC0;//XT2OFF , LFXT1 in High frequency mode (0X87 for DCO)//
> BCSCTL2=0xC0; //LFXT1 Clock source & MCLK = LFXT1/1 (0X40)//
>

---------------------------------
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Thanks....I will try that now.....I haven;t done that one....i will try now...

old_cow_yellow wrote: You need to clear OFIFG **and make sure that it stays clear** before
you use the 8MHz clock as MCLK.

If you clear OFIFG when the 8MHz clock is not stable yet, OFIFG will
stay cleared for some duration of time, but it will become set again
later.

Did you try to clear OFIFG?

TI provided examples of how you can do it correctly. But the
c-compiler may remove the delay and that makes it incorrect. Check the
compiled code.

You do not need to set the SCGO bit in SR register. If you do need to
do it, while do you use a c-compiler that does not let you do it? You
use tools to save your own effort. But you seem to get the opposite
result and wasted a lot of effort.

--- In m..., "europus" wrote:
>
> Hi all,
> After a long battle i got the high frequency clock (8MHz)
> from LFXT1 produced at P5.6(Aclk). I am still not able to
> configure MCLK = LFXT1 and MCLK still operates from DCO.
> The only thing now remaining besides configuring clock
> registers as below is setting SCG0 bit in SR.Has anyone
> gone through this pain?? I want to confirm that you "can"
> write to SR. I am using Imagecraft compiler and header file
> has no definition for Status register, though SCG0 is defined
> as #define SCG0 (0x0040)
> Does anyone know how to write to SR or turn SCG0 =1 or
> any trick around this situation....Thanks in advance...
>
> DCOCTL=0x00; //0X40
> BCSCTL1=0xC0;//XT2OFF , LFXT1 in High frequency mode (0X87 for DCO)//
> BCSCTL2=0xC0; //LFXT1 Clock source & MCLK = LFXT1/1 (0X40)//
>

---------------------------------
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